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Data update

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Ingy döt Net 2026-02-01 16:33:20 -08:00
parent 5150844a7d
commit 4bb20c9b71
7735 changed files with 38060 additions and 199180 deletions
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14
Task/Gray-code/VHDL/gray-code-1.vhdl
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity b2g is
port( bin : in std_logic_vector (4 downto 0);
gray : out std_logic_vector (4 downto 0)
);
end b2g ;
architecture rtl of b2g is
constant N : integer := bin'high;
begin
gray <= bin(n) & ( bin(N-1 downto 0) xor bin(N downto 1));
end architecture rtl;

17
Task/Gray-code/VHDL/gray-code-2.vhdl
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity g2b is
port( gray : in std_logic_vector (4 downto 0);
bin : buffer std_logic_vector (4 downto 0)
);
end g2b ;
architecture rtl of g2b is
constant N : integer := bin'high;
begin
bin(N) <= gray(N);
gen_xor: for i in N-1 downto 0 generate
bin(i) <= gray(i) xor bin(i+1);
end generate;
end architecture rtl;