Another update from ingydotnet^djgoku

Task/Four-bit-adder/Julia/four-bit-adder-1.julia

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+xor{T<:Bool}(a::T, b::T) = (a&~b)|(~a&b)
+
+halfadder{T<:Bool}(a::T, b::T) = (xor(a,b), a&b)
+
+function fulladder{T<:Bool}(a::T, b::T, c::T=false)
+    (s, ca) = halfadder(c, a)
+    (s, cb) = halfadder(s, b)
+    (s, ca|cb)
+end
+
+function adder(a::BitArray{1}, b::BitArray{1}, c0::Bool=false)
+    len = length(a)
+    length(b) == len || error("Addend width mismatch.")
+    c = c0
+    s = falses(len)
+    for i in 1:len
+        (s[i], c) = fulladder(a[i], b[i], c)
+    end
+    (s, c)
+end
+
+function adder{T<:Integer}(m::T, n::T, wid::T=4, c0::Bool=false)
+    a = bitpack(digits(m, 2, wid))[1:wid]
+    b = bitpack(digits(n, 2, wid))[1:wid]
+    adder(a, b, c0)
+end
+
+Base.bits(n::BitArray{1}) = join(reverse(int(n)), "")

Task/Four-bit-adder/Julia/four-bit-adder-2.julia

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+xavail = trues(15,15)
+xcnt = 0
+xgoal = 10
+println("Testing adder with 4-bit words:")
+while xcnt < xgoal
+    m = rand(1:15)
+    n = rand(1:15)
+    xavail[m,n] || continue
+    xavail[m,n] = xavail[n,m] = false
+    xcnt += 1
+    (s, c) = adder(m, n)
+    oflow = c ? "*" : ""
+    print(@sprintf "    %2d + %2d = %2d => " m n m+n)
+    println(@sprintf("%s + %s = %s%s",
+                     bits(m)[end-3:end],
+                     bits(n)[end-3:end],
+                     bits(s), oflow))
+end

Task/Four-bit-adder/Lua/four-bit-adder.lua

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+-- Build XOR from AND, OR and NOT
+function xor (a, b)
+	return (a and not b) or (b and not a)
+end
+
+-- Can make half adder now XOR exists
+function halfAdder (a, b)
+	local sum, carry
+	sum = xor(a, b)
+	carry = a and b
+	return sum, carry
+end
+
+-- Full adder is two half adders with carry outputs OR'd
+function fullAdder (a, b, cIn)
+	local ha0s, ha0c = halfAdder(cIn, a)
+	local ha1s, ha1c = halfAdder(ha0s, b)
+	local cOut, s = ha0c or ha1c, ha1s
+	return cOut, s
+end
+
+-- Carry bits 'ripple' through adders, first returned value is overflow
+function fourBitAdder (a3, a2, a1, a0, b3, b2, b1, b0) -- LSB-first
+	local fa0c, fa0s = fullAdder(a0, b0, false)
+	local fa1c, fa1s = fullAdder(a1, b1, fa0c)
+	local fa2c, fa2s = fullAdder(a2, b2, fa1c)
+	local fa3c, fa3s = fullAdder(a3, b3, fa2c)
+	return fa3c, fa3s, fa2s, fa1s, fa0s -- Return as MSB-first
+end
+
+-- Take string of noughts and ones, convert to native boolean type
+function toBool (bitString)
+	local boolList, bit = {}
+	for digit = 1, 4 do
+		bit = string.sub(string.format("%04d", bitString), digit, digit)
+		if bit == "0" then table.insert(boolList, false) end
+		if bit == "1" then table.insert(boolList, true) end
+	end
+	return boolList
+end
+
+-- Take list of booleans, convert to string of binary digits (variadic)
+function toBits (...)
+	local bitString = ""
+	for i, bool in pairs{...} do
+		if bool then
+			bitString = bitString .. "1"
+		else
+			bitString = bitString .. "0"
+		end
+	end
+	return bitString
+end
+
+-- Little driver function to neaten use of the adder
+function add (n1, n2)
+	local A, B = toBool(n1), toBool(n2)
+	local v, s0, s1, s2, s3 = fourBitAdder	(	A[1], A[2], A[3], A[4],
+							B[1], B[2], B[3], B[4]
+						)
+	return toBits(s0, s1, s2, s3), v
+end
+
+-- Main procedure (usage examples)
+print("SUM", "OVERFLOW\n")
+print(add(0001, 0001)) -- 1 + 1 = 2
+print(add(0101, 1010)) -- 5 + 10 = 15
+print(add(0000, 1111)) -- 0 + 15 = 15
+print(add(0001, 1111)) -- 1 + 15 = 16 (causes overflow)

Task/Four-bit-adder/Verilog/four-bit-adder.v

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+module Half_Adder( output c, s, input a, b );
+  xor xor01 (s, a, b);
+  and and01 (c, a, b);
+endmodule // Half_Adder
+
+module Full_Adder( output c_out, s, input a, b, c_in );
+
+  wire s_ha1, c_ha1, c_ha2;
+
+  Half_Adder ha01( c_ha1, s_ha1, a, b );
+  Half_Adder ha02( c_ha2, s, s_ha1, c_in );
+  or or01 ( c_out, c_ha1, c_ha2 );
+
+endmodule // Full_Adder
+
+module Full_Adder4( output [4:0] s, input [3:0] a, b, input c_in );
+
+  wire [4:0] c;
+
+  Full_Adder adder00 ( c[1], s[0], a[0], b[0], c_in );
+  Full_Adder adder01 ( c[2], s[1], a[1], b[1], c[1] );
+  Full_Adder adder02 ( c[3], s[2], a[2], b[2], c[2] );
+  Full_Adder adder03 ( c[4], s[3], a[3], b[3], c[3] );
+
+  assign s[4] = c[4];
+
+endmodule // Full_Adder4
+
+module test_Full_Adder();
+
+  reg  [3:0] a;
+  reg  [3:0] b;
+  wire [4:0] s;
+
+  Full_Adder4 FA4 ( s, a, b, 0 );
+
+  initial begin
+    $display( "   a +    b =     s" );
+    $monitor( "%4d + %4d = %5d", a, b, s );
+     a=4'b0000; b=4'b0000;
+  #1 a=4'b0000; b=4'b0001;
+  #1 a=4'b0001; b=4'b0001;
+  #1 a=4'b0011; b=4'b0001;
+  #1 a=4'b0111; b=4'b0001;
+  #1 a=4'b1111; b=4'b0001;
+  end
+
+endmodule // test_Full_Adder