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September 2017 Update

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Ingy döt Net 2017-09-23 10:01:46 +02:00
parent bba7bfd280
commit ba8067c3b7
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Task/Loops-Break/360-Assembly/loops-break.360 Normal file
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* Loops Break 15/02/2017
LOOPBREA CSECT
USING LOOPBREA,R13 base register
B 72(R15) skip savearea
DC 17F'0' savearea
STM R14,R12,12(R13) prolog
ST R13,4(R15) " <-
ST R15,8(R13) " ->
LR R13,R15 " addressability
LOOP MVC PG,=CL80' ' clean buffer
LA R8,PG ipg=0
BAL R14,RANDINT call randint
C R6,=F'10' if k=10 then leave
BE ENDLOOP <-- loop break
BAL R14,RANDINT call randint
XPRNT PG,L'PG print buffer
B LOOP loop forever
ENDLOOP XPRNT PG,L'PG print buffer
L R13,4(0,R13) epilog
LM R14,R12,12(R13) " restore
XR R15,R15 " rc=0
BR R14 exit
RANDINT L R5,RANDSEED randint
M R4,=F'397204091' "
D R4,=X'7FFFFFFF' "
ST R4,RANDSEED "
LR R5,R4 "
SR R4,R4 "
D R4,=F'20' "
LR R6,R4 k=randint(20)
XDECO R6,XDEC edit k
MVC 0(4,R8),XDEC+8 output k
LA R8,4(R8) ipg=ipg+4
BR R14 return
RANDSEED DC F'39710831' seed
PG DS CL80 buffer
XDEC DS CL12
YREGS
END LOOPBREA