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Task/Arrays/VHDL/arrays.vhdl
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57
Task/Arrays/VHDL/arrays.vhdl
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entity Array_Test is
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end entity Array_Test;
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architecture Example of Array_test is
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-- Array type have to be defined first
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type Integer_Array is array (Integer range <>) of Integer;
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-- Array index range can be ascending...
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signal A : Integer_Array (1 to 20);
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-- or descending
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signal B : Integer_Array (20 downto 1);
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-- VHDL array index ranges may begin at any value, not just 0 or 1
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signal C : Integer_Array (-37 to 20);
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-- VHDL arrays may be indexed by enumerated types, which are
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-- discrete non-numeric types
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type Days is (Mon, Tue, Wed, Thu, Fri, Sat, Sun);
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type Activities is (Work, Fish);
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type Daily_Activities is array (Days) of Activities;
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signal This_Week : Daily_Activities := (Mon to Fri => Work, Others => Fish);
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type Finger is range 1 to 4; -- exclude thumb
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type Fingers_Extended is array (Finger) of Boolean;
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signal Extended : Fingers_Extended;
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-- Array types may be unconstrained.
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-- Objects of the type must be constrained
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type Arr is array (Integer range <>) of Integer;
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signal Uninitialized : Arr (1 to 10);
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signal Initialized_1 : Arr (1 to 20) := (others => 1);
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constant Initialized_2 : Arr := (1 to 30 => 2);
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constant Const : Arr := (1 to 10 => 1, 11 to 20 => 2, 21 | 22 => 3);
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signal Centered : Arr (-50 to 50) := (0 => 1, others => 0);
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signal Result : Integer;
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begin
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A <= (others => 0); -- Assign whole array
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B <= (1 => 1, 2 => 1,
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3 => 2, others => 0); -- Assign whole array, different values
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A (1) <= -1; -- Assign individual element
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A (2 to 4) <= B (3 downto 1); -- Assign a slice
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A (3 to 5) <= (2, 4, -1); -- Assign an aggregate
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A (3 to 5) <= A (4 to 6); -- It is OK to overlap slices when assigned
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-- VHDL arrays does not have 'first' and 'last' elements,
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-- but have 'Left' and 'Right' instead
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Extended (Extended'Left) <= False; -- Set leftmost element of array
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Extended (Extended'Right) <= False; -- Set rightmost element of array
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Result <= A (A'Low) + B (B'High);
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end architecture Example;
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