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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 7387c8f97b
commit cb5bb5e222
199093 changed files with 3378972 additions and 0 deletions
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2
Task/Conditional-structures/Verilog/conditional-structures-1.v Normal file
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if( expr_booleana ) command1;
else command2;

6
Task/Conditional-structures/Verilog/conditional-structures-2.v Normal file
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case( expr_booleana )
valor1: command1;
valor2: command2;
...
default: commandN;
endcase