Data commit

Task/Four-bit-adder/SystemVerilog/four-bit-adder-1.v

@@ -0,0 +1,33 @@
+module Half_Adder( input a, b, output s, c );
+  assign s = a ^ b;
+  assign c = a & b;
+endmodule
+
+module Full_Adder( input a, b, c_in, output s, c_out );
+
+  wire s_ha1, c_ha1, c_ha2;
+
+  Half_Adder ha1( .a(c_in), .b(a), .s(s_ha1), .c(c_ha1) );
+  Half_Adder ha2( .a(s_ha1), .b(b), .s(s), .c(c_ha2) );
+  assign c_out = c_ha1 | c_ha2;
+
+endmodule
+
+
+module Multibit_Adder(a,b,s);
+  parameter N = 8;
+  input [N-1:0] a;
+  input [N-1:0] b;
+  output [N:0] s;
+
+  wire [N:0] c;
+
+  assign c[0] = 0;
+  assign s[N] = c[N];
+
+  generate
+    genvar I;
+    for (I=0; I<N; ++I) Full_Adder add( .a(a[I]), .b(b[I]), .s(s[I]), .c_in(c[I]), .c_out(c[I+1]) );
+  endgenerate
+
+endmodule

Task/Four-bit-adder/SystemVerilog/four-bit-adder-2.v

@@ -0,0 +1,30 @@
+module simTop();
+
+  bit [3:0] a;
+  bit [3:0] b;
+  bit [4:0] s;
+
+  Multibit_Adder#(4) adder(.*);
+
+  always_comb begin
+    $display( "%d + %d = %d", a, b, s );
+    assert( s == a+b );
+  end
+
+endmodule
+
+program Main();
+
+  class Test;
+    rand bit [3:0] a;
+    rand bit [3:0] b;
+  endclass
+
+  Test t = new;
+  initial repeat (20) begin
+    #10 t.randomize;
+    simTop.a = t.a;
+    simTop.b = t.b;
+  end
+
+endprogram