Data commit

Task/Four-bit-adder/Zkl/four-bit-adder-1.zkl

@@ -0,0 +1,24 @@
+fcn xor(a,b) // a,b are 1|0 -->a^b(1|0)
+   { a.bitAnd(b.bitNot()).bitOr(b.bitAnd(a.bitNot())) }
+
+fcn halfAdder(a,b) // -->(carry, a+b) (1|0)
+   { return(a.bitAnd(b), xor(a,b)) }
+
+fcn fullBitAdder(c, a,b){ //-->(carry, a+b+c), a,b,c are 1|0
+   c1,s := halfAdder(a,c);
+   c2,s := halfAdder(s,b);
+   c3   := c1.bitOr(c2);
+   return(c3,s);
+}
+
+   // big endian
+fcn fourBitAdder(a3,a2,a1,a0, b3,b2,b1,b0){ //-->(carry, s3,s2,s1,s0)
+   c,s0 := fullBitAdder(0, a0,b0);
+   c,s1 := fullBitAdder(c, a1,b1);
+   c,s2 := fullBitAdder(c, a2,b2);
+   c,s3 := fullBitAdder(c, a3,b3);
+   return(c, s3,s2,s1,s0);
+}
+
+// add(10,9)  result should be 1 0 0 1 1 (0x13, 3 carry 1)
+println(fourBitAdder(1,0,1,0, 1,0,0,1));

Task/Four-bit-adder/Zkl/four-bit-adder-2.zkl

@@ -0,0 +1,8 @@
+fcn nBitAddr(as,bs){ //-->(carry, sn..s3,s2,s1,s0)
+   (ss:=List()).append(
+      [as.len()-1 .. 0,-1].reduce('wrap(c,n){
+         c2,s:=fullBitAdder(c,as[n],bs[n]); ss + s; c2
+      },0))
+   .reverse();
+}
+println(nBitAddr(T(1,0,1,0), T(1,0,0,1)));