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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 7387c8f97b
commit cb5bb5e222
199093 changed files with 3378972 additions and 0 deletions

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MULTIPLY: STX MULN ; 6502 has no "acc += xreg" instruction,
TXA ; so use a memory address
MULLOOP: DEY
CLC ; remember to clear the carry flag before
ADC MULN ; doing addition or subtraction
CPY #$01
BNE MULLOOP
RTS

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; https://skilldrick.github.io/easy6502/
; Multiplies A by X
define memory 1040
JMP MAIN
MULTIPLY: STA memory ; memory = A
BEQ MUL_END ; A = 0
TXA ; A = X
BEQ MUL_END ; X = 0 -> A = 0
LDA memory
CLC
MUL_LOOP: DEX ; X -= 1
BEQ MUL_END ; X = 0 -> A = A * X
ADC memory ; A += memory
JMP MUL_LOOP
MUL_END: RTS
MAIN: LDA #50
LDX #5
JSR MULTIPLY