Data commit

Task/Gray-code/VHDL/gray-code-1.vhdl

@@ -0,0 +1,14 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity b2g is
+   port(  bin  : in  std_logic_vector (4 downto 0);
+          gray : out std_logic_vector (4 downto 0)
+        );
+end b2g ;
+
+architecture rtl of b2g is
+  constant N : integer := bin'high;
+begin
+  gray <= bin(n) & ( bin(N-1 downto 0) xor bin(N downto 1));
+end architecture rtl;

Task/Gray-code/VHDL/gray-code-2.vhdl

@@ -0,0 +1,17 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity g2b is
+   port(  gray : in     std_logic_vector (4 downto 0);
+          bin  : buffer std_logic_vector (4 downto 0)
+        );
+end g2b ;
+
+architecture rtl of g2b is
+  constant N : integer := bin'high;
+begin
+  bin(N) <= gray(N);
+  gen_xor: for i in N-1 downto 0 generate
+    bin(i) <= gray(i) xor bin(i+1);
+  end generate;
+end architecture rtl;