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Ingy döt Net 2023-07-01 11:58:00 -04:00
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Task/Logical-operations/Verilog/logical-operations.v Normal file
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module main;
integer a, b;
initial begin
a = 1; //true
b = 0; //false
$display(a && b); //AND
$display(a || b); //OR
$display(!a); //NOT
$finish ;
end
endmodule