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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 7387c8f97b
commit cb5bb5e222
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Task/Loops-Do-while/Verilog/loops-do-while.v Normal file
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module main;
integer i;
initial begin
i = 1;
$write(i);
while(i % 6 != 0) begin
i = i + 1;
$write(i);
end
$finish ;
end
endmodule