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Ingy döt Net 2023-07-01 11:58:00 -04:00
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Task/Loops-N-plus-one-half/Verilog/loops-n-plus-one-half.v Normal file
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module main;
integer i;
initial begin
for(i = 1; i <= 10; i = i + 1) begin
$write(i);
if (i < 10 ) $write(", ");
end
$display("");
$finish ;
end
endmodule