Data commit

2023-07-01 11:58:00 -04:00 · 2023-07-01 11:58:00 -04:00 · cb5bb5e222
commit cb5bb5e222
parent 7387c8f97b
199093 changed files with 3378972 additions and 0 deletions
--- a/Task/Loops-While/Verilog/loops-while.v
+++ b/Task/Loops-While/Verilog/loops-while.v
@ -0,0 +1,13 @@
+module main;
+  integer i;
+
+  initial begin
+      i = 1024;
+
+      while( i > 0) begin
+        $display(i);
+        i = i / 2;
+      end
+      $finish ;
+    end
+endmodule