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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 7387c8f97b
commit cb5bb5e222
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2
Task/Memory-layout-of-a-data-structure/00-META.yaml Normal file
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---
from: http://rosettacode.org/wiki/Memory_layout_of_a_data_structure

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Task/Memory-layout-of-a-data-structure/00-TASK.txt Normal file
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It is often useful to control the memory layout of fields in a data structure to match an interface control definition, or to interface with hardware. Define a data structure matching the RS-232 Plug Definition. Use the 9-pin definition for brevity.
Pin Settings for Plug
(Reverse order for socket.)
__________________________________________
1 2 3 4 5 6 7 8 9 10 11 12 13
14 15 16 17 18 19 20 21 22 23 24 25
_________________
1 2 3 4 5
6 7 8 9
25 pin 9 pin
1 - PG Protective ground
2 - TD Transmitted data 3
3 - RD Received data 2
4 - RTS Request to send 7
5 - CTS Clear to send 8
6 - DSR Data set ready 6
7 - SG Signal ground 5
8 - CD Carrier detect 1
9 - + voltage (testing)
10 - - voltage (testing)
11 -
12 - SCD Secondary CD
13 - SCS Secondary CTS
14 - STD Secondary TD
15 - TC Transmit clock
16 - SRD Secondary RD
17 - RC Receiver clock
18 -
19 - SRS Secondary RTS
20 - DTR Data terminal ready 4
21 - SQD Signal quality detector
22 - RI Ring indicator 9
23 - DRS Data rate select
24 - XTC External clock
25 -

2
Task/Memory-layout-of-a-data-structure/6502-Assembly/memory-layout-of-a-data-structure-1.6502 Normal file
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soft_rs232_lo equ $20 ;%87654321
soft_rs232_hi equ $21 ;%-------9

3
Task/Memory-layout-of-a-data-structure/6502-Assembly/memory-layout-of-a-data-structure-2.6502 Normal file
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LDA soft_rs232_lo
ora #%00000100
sta soft_rs232_lo

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Task/Memory-layout-of-a-data-structure/68000-Assembly/memory-layout-of-a-data-structure-1.68000 Normal file
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BIT_0 equ $1
BIT_1 equ $2
BIT_2 equ $4
BIT_3 equ $8
BIT_4 equ $10
BIT_5 equ $20
BIT_6 equ $40
BIT_7 equ $80
BIT_8 equ $100
BIT_9 equ $200
RS232_9_TD equ BIT_3
RS232_9_RD equ BIT_2
RS232_9_RTS equ BIT_7
RS232_9_CTS equ BIT_8
RS232_9_DSR equ BIT_6
RS232_9_SG equ BIT_5
RS232_9_CD equ BIT_1

5
Task/Memory-layout-of-a-data-structure/68000-Assembly/memory-layout-of-a-data-structure-2.68000 Normal file
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rs232_9pin_port equ $A00000
;I chose $A00000 arbitrarily as an example, its actual address depends on the wiring.
MOVE.W #RS232_9_CTS,rs232_9pin_port
MOVE.W #RS232_9_CTS|RS232_9_RD|RS232_9_SG,rs232_9pin_port ;bitwise OR can be used at compile time to combine the labels.

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Task/Memory-layout-of-a-data-structure/ALGOL-68/memory-layout-of-a-data-structure.alg Normal file
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MODE RSTWOTHREETWO = BITS;
INT ofs = bits width - 9;
INT
lwb rs232 = ofs + 1,
carrier detect = ofs + 1,
received data = ofs + 2,
transmitted data = ofs + 3,
data terminal ready = ofs + 4,
signal ground = ofs + 5,
data set ready = ofs + 6,
request to send = ofs + 7,
clear to send = ofs + 8,
ring indicator = ofs + 9,
upb rs232 = ofs + 9;
RSTWOTHREETWO rs232 bits := 2r10000000; # up to bits width, OR #
print(("received data: ",received data ELEM rs232bits, new line));
rs232 bits := bits pack((FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE));
print(("received data: ",received data ELEM rs232bits, new line))

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Task/Memory-layout-of-a-data-structure/Ada/memory-layout-of-a-data-structure.ada Normal file
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type Bit is mod 2;
type Rs_232_Layout is record
Carrier_Detect : Bit;
Received_Data : Bit;
Transmitted_Data : Bit;
Data_Terminal_ready : Bit;
Signal_Ground : Bit;
Data_Set_Ready : Bit;
Request_To_Send : Bit;
Clear_To_Send : Bit;
Ring_Indicator : Bit;
end record;
for Rs_232_Layout use record
Carrier_Detect at 0 range 0..0;
Received_Data at 0 range 1..1;
Transmitted_Data at 0 range 2..2;
Data_Terminal_Ready at 0 range 3..3;
Signal_Ground at 0 range 4..4;
Data_Set_Ready at 0 range 5..5;
Request_To_Send at 0 range 6..6;
Clear_To_Send at 0 range 7..7;
Ring_Indicator at 0 range 8..8;
end record;

12
Task/Memory-layout-of-a-data-structure/C/memory-layout-of-a-data-structure.c Normal file
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struct RS232_data
{
unsigned carrier_detect : 1;
unsigned received_data : 1;
unsigned transmitted_data : 1;
unsigned data_terminal_ready : 1;
unsigned signal_ground : 1;
unsigned data_set_ready : 1;
unsigned request_to_send : 1;
unsigned clear_to_send : 1;
unsigned ring_indicator : 1;
};

71
Task/Memory-layout-of-a-data-structure/D/memory-layout-of-a-data-structure-1.d Normal file
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module controlFieldsInStruct;
import tango.core.BitArray;
import tango.io.Stdout;
import tango.text.convert.Integer;
class RS232Wrapper(int Length = 9)
{
static assert(Length == 9 || Length == 25, "ERROR, wrong type");
BitArray ba;
static uint[char[]] _map;
public:
static if (Length == 9) {
static this() {
_map = [ cast(char[])
"CD" : 1, "RD" : 2, "TD" : 3, "DTR" : 4, "SG" : 5,
"DSR" : 6, "RTS" : 7, "CTS" : 8, "RI" : 9
];
}
} else {
static this() {
_map = [ cast(char[])
"PG" : 1u, "TD" : 2, "RD" : 3, "RTS" : 4, "CTS" : 5,
"DSR" : 6, "SG" : 7, "CD" : 8, "+" : 9, "-" : 10,
"SCD" : 12, "SCS" : 13, "STD" : 14, "TC" : 15, "SRD" : 16,
"RC" : 17, "SRS" : 19, "DTR" : 20, "SQD" : 21, "RI" : 22,
"DRS" : 23, "XTC" : 24
];
}
}
this() {
ba.length = Length;
}
bool opIndex(uint pos) { return ba[pos]; }
bool opIndexAssign(bool b, uint pos) { return (ba[pos] = b); }
bool opIndex(char[] name) {
assert (name in _map, "don't know that plug: " ~ name);
return opIndex(_map[name]);
}
bool opIndexAssign(bool b, char[] name) {
assert (name in _map, "don't know that plug: " ~ name);
return opIndexAssign(b, _map[name]);
}
void opSliceAssign(bool b) { foreach (ref r; ba) r = b; }
char[] toString() {
char[] ret = "[";
foreach (name, value; _map)
ret ~= name ~ ":" ~ (ba[value]?"1":"0") ~", ";
ret ~= "]";
return ret;
}
}
int main(char[][] args)
{
auto ba = new RS232Wrapper!(25);
// set all bits
ba[] = 1;
ba["RD"] = 0;
ba[5] = 0;
Stdout (ba).newline;
return 0;
}

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Task/Memory-layout-of-a-data-structure/D/memory-layout-of-a-data-structure-2.d Normal file
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import std.bitmanip;
struct RS232_data {
static if (std.system.endian == std.system.Endian.bigEndian) {
mixin(bitfields!(bool, "carrier_detect", 1,
bool, "received_data", 1,
bool, "transmitted_data", 1,
bool, "data_terminal_ready", 1,
bool, "signal_ground", 1,
bool, "data_set_ready", 1,
bool, "request_to_send", 1,
bool, "clear_to_send", 1,
bool, "ring_indicator", 1,
bool, "", 7));
} else {
mixin(bitfields!(bool, "", 7,
bool, "ring_indicator", 1,
bool, "clear_to_send", 1,
bool, "request_to_send", 1,
bool, "data_set_ready", 1,
bool, "signal_ground", 1,
bool, "data_terminal_ready", 1,
bool, "transmitted_data", 1,
bool, "received_data", 1,
bool, "carrier_detect", 1));
}
static assert(RS232_data.sizeof == 2);
}
void main() {}

37
Task/Memory-layout-of-a-data-structure/Delphi/memory-layout-of-a-data-structure.delphi Normal file
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{Enumerate pin assignments}
type TRS232Pins = (rpCarrierDetect, rpReceivedData, rpTransmittedData,
rpDataTerminalReady, rpSignalGround, rpDataSetReady,
rpRequestToSend, rpClearToSend, rpRingIndicator);
{Make into a set}
type TPinSet = set of TRS232Pins;
var Pins: TPinSet; {Global variable holding a set of pins}
procedure ShowMemory(Memo: TMemo; Name: string; SetPins: TPinSet);
{Extract the set data from memory and display it}
var S: string;
var P: PWord;
begin
P:=@Pins;
Pins:=SetPins;
S:=Name;
S:=S+IntToBin(P^, 16, True);
Memo.Lines.Add(S);
end;
procedure ShowPinsMemory(Memo: TMemo);
begin
ShowMemory(Memo,'Empty: ',[]);
ShowMemory(Memo,'Carrier Detect: ',[rpCarrierDetect]);
ShowMemory(Memo,'Received Data: ',[rpReceivedData]);
ShowMemory(Memo,'Transmitted Data: ',[rpTransmittedData]);
ShowMemory(Memo,'Data Terminal Ready:',[rpDataTerminalReady]);
ShowMemory(Memo,'Signal Ground: ',[rpSignalGround]);
ShowMemory(Memo,'Data Set Ready: ',[rpDataSetReady]);
ShowMemory(Memo,'Request To Send: ',[rpRequestToSend]);
ShowMemory(Memo,'Clear To Send: ',[rpClearToSend]);
ShowMemory(Memo,'Ring Indicator: ',[rpRingIndicator]);
end;

3
Task/Memory-layout-of-a-data-structure/Forth/memory-layout-of-a-data-structure-1.fth Normal file
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: masks ( n -- ) 0 do 1 i lshift constant loop ;
9 masks DCD RxD TxD DTR SG DSR RTS CTS RI

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Task/Memory-layout-of-a-data-structure/Forth/memory-layout-of-a-data-structure-2.fth Normal file
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hex
3fd constant com1-ctrl
decimal
: wait-ready
begin
com1-ctrl in
CTS and
until ;
: wait-rx
begin
com1-ctrl in
CTS and 0=
until ;
: send-byte ( b -- ) \ send assuming N81 (no parity, 8 bits data, 1 bit frame)
255 and
9 0 do
RTS com1-ctrl out
wait-ready
dup 1 and if TxD else 0 then com1-ctrl out
wait-rx
2/
loop drop ;

11
Task/Memory-layout-of-a-data-structure/Fortran/memory-layout-of-a-data-structure.f Normal file
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TYPE RS232PIN9
LOGICAL CARRIER_DETECT !1
LOGICAL RECEIVED_DATA !2
LOGICAL TRANSMITTED_DATA !3
LOGICAL DATA_TERMINAL_READY !4
LOGICAL SIGNAL_GROUND !5
LOGICAL DATA_SET_READY !6
LOGICAL REQUEST_TO_SEND !7
LOGICAL CLEAR_TO_SEND !8
LOGICAL RING_INDICATOR !9
END TYPE RS232PIN9

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Task/Memory-layout-of-a-data-structure/Free-Pascal/memory-layout-of-a-data-structure.pas Normal file
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program rs232(input, output, stdErr);
type
{$packEnum 2}{$scopedEnums off}
pin = (carrierDetect, receivedData, transmittedData, dataTerminalReady,
signalGround, dataSetReady, requestToSend, clearToSend, ringIndicator);
{$packSet 2}
pins = set of pin;
var
signal: pins;
// for demonstration purposes, in order to reveal the memory layout
signalMemoryStructure: word absolute signal;
{$if sizeOf(signal) <> sizeOf(word)} // just as safe-guard
{$fatal signal size}
{$endIf}
begin
signal := [];
include(signal, signalGround); // equivalent to signal := signal + [signalGround];
// for demonstration purposes: obviously we know this is always `true`
if signalGround in signal then
begin
writeLn(binStr(signalMemoryStructure, bitSizeOf(signal)));
end;
end.

17
Task/Memory-layout-of-a-data-structure/FreeBASIC/memory-layout-of-a-data-structure.basic Normal file
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' FB 1.05.0 Win64
' using bit fields
Type RS232_Pin9
carrierDetect : 1 As UByte
receivedData : 1 As UByte
transmittedData : 1 As UByte
dataTerminalReady : 1 As UByte
signalGround : 1 As UByte
dataSetReady : 1 As UByte
requestToSend : 1 As UByte
clearToSend : 1 As UByte
ringIndicator : 1 As UByte
End Type
Print SizeOf(RS232_Pin9) '' 2 bytes
Sleep

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Task/Memory-layout-of-a-data-structure/Go/memory-layout-of-a-data-structure.go Normal file
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package main
import "fmt"
type rs232p9 uint16
const (
CD9 rs232p9 = 1 << iota // Carrier detect
RD9 // Received data
TD9 // Transmitted data
DTR9 // Data terminal ready
SG9 // signal ground
DSR9 // Data set ready
RTS9 // Request to send
CTS9 // Clear to send
RI9 // Ring indicator
)
func main() {
// set some nonsense bits just for example
p := RI9 | TD9 | CD9
fmt.Printf("Type=%T value=%#04x\n", p, p)
}

14
Task/Memory-layout-of-a-data-structure/J/memory-layout-of-a-data-structure-1.j Normal file
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default=: 0#~#|:'labels comments'=:|:(4 ({.@;:@{. ; }.)]);._2 {{)n
RD Received data
TD Transmitted data
DTR Data terminal ready
SG Signal ground
DSR Data set ready
RTS Request to send
CTS Clear to send
RI Ring indicator
}}
indices=: labels (i. ;: ::]) ]
ndx=: [ {~ [ indices ]
asgn=: {{ y (x indices m)} x }}

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Task/Memory-layout-of-a-data-structure/J/memory-layout-of-a-data-structure-2.j Normal file
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example=: default NB. new instance
example ndx 'RI CTS'
0 0
example=: example 'RI RTS TD' asgn 1 2 3
example ndx 'RI CTS'
1 0

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Task/Memory-layout-of-a-data-structure/Julia/memory-layout-of-a-data-structure.julia Normal file
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mutable struct NinePinSerialPort
pins::BitArray
function NinePinSerialPort()
this = new()
this.pins = BitArray(9)
end
end
const CD = 1
const RD = 2
const TD = 3
const SG = 5
const DSR = 6
const RTS = 7
const CTS = 8
# Here we test the type's code.
port = NinePinSerialPort()
println("Port is now at defaults, which are $port")
port[CTS] = true
println("CD pin of port, which is pin $CD, is now $(port[CD])")
println("CTS pin of port, which is pin $CTS, is now $(port[CTS])")
println("port is now: $port")

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Task/Memory-layout-of-a-data-structure/Kotlin/memory-layout-of-a-data-structure.kotlin Normal file
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// version 1.0.6
const val OFF = false
const val ON = true
fun toOnOff(b: Boolean) = if (b) "ON" else "OFF"
data class Rs232Pins9(
var carrierDetect : Boolean = OFF,
var receivedData : Boolean = OFF,
var transmittedData : Boolean = OFF,
var dataTerminalReady : Boolean = OFF,
var signalGround : Boolean = OFF,
var dataSetReady : Boolean = OFF,
var requestToSend : Boolean = OFF,
var clearToSend : Boolean = OFF,
var ringIndicator : Boolean = OFF
) {
fun setPin(n: Int, v: Boolean) {
when (n) {
1 -> carrierDetect = v
2 -> receivedData = v
3 -> transmittedData = v
4 -> dataTerminalReady = v
5 -> signalGround = v
6 -> dataSetReady = v
7 -> requestToSend = v
8 -> clearToSend = v
9 -> ringIndicator = v
}
}
}
fun main(args: Array<String>) {
val plug = Rs232Pins9(carrierDetect = ON, receivedData = ON) // set first two pins, say
println(toOnOff(plug.component2())) // print value of pin 2 by number
plug.transmittedData = ON // set pin 3 by name
plug.setPin(4, ON) // set pin 4 by number
println(toOnOff(plug.component3())) // print value of pin 3 by number
println(toOnOff(plug.dataTerminalReady)) // print value of pin 4 by name
println(toOnOff(plug.ringIndicator)) // print value of pin 9 by name
}

35
Task/Memory-layout-of-a-data-structure/MATLAB/memory-layout-of-a-data-structure.m Normal file
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>> rs232 = struct('carrier_detect', logical(1),...
'received_data' , logical(1), ...
'transmitted_data', logical(1),...
'data_terminal_ready', logical(1),...
'signal_ground', logical(1),...
'data_set_ready', logical(1),...
'request_to_send', logical(1),...
'clear_to_send', logical(1),...
'ring_indicator', logical(1))
rs232 =
carrier_detect: 1
received_data: 1
transmitted_data: 1
data_terminal_ready: 1
signal_ground: 1
data_set_ready: 1
request_to_send: 1
clear_to_send: 1
ring_indicator: 1
>> struct2cell(rs232)
ans =
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]

70
Task/Memory-layout-of-a-data-structure/Mercury/memory-layout-of-a-data-structure-1.mercury Normal file
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:- module rs232.
:- interface.
:- import_module bool, io, list, string.
:- type rs232_pin
---> carrier_detect
; received_data
; transmitted_data
; data_terminal_ready
; signal_ground
; data_set_ready
; request_to_send
; clear_to_send
; ring_indicator.
:- type rs232.
:- func rs232_bits = rs232.
:- func rs232_bits(bool) = rs232.
:- func rs232_set(rs232, rs232_pin) = rs232.
:- func rs232_clear(rs232, rs232_pin) = rs232.
:- pred rs232_is_set(rs232::in, rs232_pin::in) is semidet.
:- pred rs232_is_clear(rs232::in, rs232_pin::in) is semidet.
:- func rs232_set_bits(rs232, list(rs232_pin)) = rs232.
:- func rs232_clear_bits(rs232, list(rs232_pin)) = rs232.
:- func to_string(rs232) = string.
:- pred write_rs232(rs232::in, io::di, io::uo) is det.
:- implementation.
:- import_module bitmap.
:- type rs232 == bitmap.
rs232_bits = rs232_bits(no).
rs232_bits(Default) = bitmap.init(9, Default).
rs232_set(A, Pin) = unsafe_set(A, to_index(Pin)).
rs232_clear(A, Pin) = unsafe_clear(A, to_index(Pin)).
rs232_is_set(A, Pin) :- unsafe_is_set(A, to_index(Pin)).
rs232_is_clear(A, Pin) :- unsafe_is_clear(A, to_index(Pin)).
rs232_set_bits(A, Pins) = foldl((func(Pin, B) = rs232_set(B, Pin)), Pins, A).
rs232_clear_bits(A, Pins) = foldl((func(Pin, B) = rs232_clear(B, Pin)), Pins, A).
to_string(A) = bitmap.to_string(A).
write_rs232(A, !IO) :- write_bitmap(resize(A, 16, no), !IO).
% cannot write a bitmap that isn't byte-divisible
:- func to_index(rs232_pin) = bit_index.
to_index(carrier_detect) = 0.
to_index(received_data) = 1.
to_index(transmitted_data) = 2.
to_index(data_terminal_ready) = 3.
to_index(signal_ground) = 4.
to_index(data_set_ready) = 5.
to_index(request_to_send) = 6.
to_index(clear_to_send) = 7.
to_index(ring_indicator) = 8.
:- end_module rs232.

37
Task/Memory-layout-of-a-data-structure/Mercury/memory-layout-of-a-data-structure-2.mercury Normal file
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:- module rs232_main.
:- interface.
:- import_module io.
:- pred main(io::di, io::uo) is det.
:- implementation.
:- import_module bitmap, bool, list, rs232.
main(!IO) :-
Com1 = rs232_set_bits(rs232_bits, [data_terminal_ready, data_set_ready]),
Com2 = rs232_clear_bits(rs232_bits(yes), [data_terminal_ready, data_set_ready]),
write_string("Com1 bits = ", !IO),
write_string(to_string(Com1), !IO), nl(!IO),
write_string("Com2 bits = ", !IO),
write_string(to_string(Com2), !IO), nl(!IO),
write_string("Com1 DTR is ", !IO),
( if rs232_is_set(Com1, data_terminal_ready) then
write_string("set.", !IO), nl(!IO)
else
write_string("clear.", !IO), nl(!IO)
),
write_string("Com2 DSR is ", !IO),
( if rs232_is_clear(Com2, data_set_ready) then
write_string("clear.", !IO), nl(!IO)
else
write_string("set.", !IO), nl(!IO)
).
:- end_module rs232_main.

19
Task/Memory-layout-of-a-data-structure/Nim/memory-layout-of-a-data-structure.nim Normal file
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type
rs232Data = enum
carrierDetect,
receivedData,
transmittedData,
dataTerminalReady,
signalGround,
dataSetReady,
requestToSend,
clearToSend,
ringIndicator
# Bit vector of 9 bits
var bv = {carrierDetect, signalGround, ringIndicator}
echo cast[uint16](bv) # Conversion of bitvector to 2 bytes for writing
let readValue: uint16 = 123
bv = cast[set[rs232Data]](readValue) # Conversion of a read value to bitvector
echo bv

25
Task/Memory-layout-of-a-data-structure/OCaml/memory-layout-of-a-data-structure.ocaml Normal file
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open ExtLib
class rs232_data = object
val d = BitSet.create 9
method carrier_detect = BitSet.is_set d 0
method received_data = BitSet.is_set d 1
method transmitted_data = BitSet.is_set d 2
method data_terminal_ready = BitSet.is_set d 3
method signal_ground = BitSet.is_set d 4
method data_set_ready = BitSet.is_set d 5
method request_to_send = BitSet.is_set d 6
method clear_to_send = BitSet.is_set d 7
method ring_indicator = BitSet.is_set d 8
method set_carrier_detect b = (if b then BitSet.set else BitSet.unset) d 0
method set_received_data b = (if b then BitSet.set else BitSet.unset) d 1
method set_transmitted_data b = (if b then BitSet.set else BitSet.unset) d 2
method set_data_terminal_ready b = (if b then BitSet.set else BitSet.unset) d 3
method set_signal_ground b = (if b then BitSet.set else BitSet.unset) d 4
method set_data_set_ready b = (if b then BitSet.set else BitSet.unset) d 5
method set_request_to_send b = (if b then BitSet.set else BitSet.unset) d 6
method set_clear_to_send b = (if b then BitSet.set else BitSet.unset) d 7
method set_ring_indicator b = (if b then BitSet.set else BitSet.unset) d 8
end
;;

10
Task/Memory-layout-of-a-data-structure/PL-I/memory-layout-of-a-data-structure.pli Normal file
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declare 1 RS232_layout,
2 Carrier_Detect Bit(1),
2 Received_Data Bit(1),
2 Transmitted_Data Bit(1),
2 Data_Terminal_ready Bit(1),
2 Signal_Ground Bit(1),
2 Data_Set_Ready Bit(1),
2 Request_To_Send Bit(1),
2 Clear_To_Send Bit(1),
2 Ring_Indicator Bit(1);

30
Task/Memory-layout-of-a-data-structure/Perl/memory-layout-of-a-data-structure.pl Normal file
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use Bit::Vector::Minimal qw();
my $vec = Bit::Vector::Minimal->new(size => 24);
my %rs232 = reverse (
1 => 'PG Protective ground',
2 => 'TD Transmitted data',
3 => 'RD Received data',
4 => 'RTS Request to send',
5 => 'CTS Clear to send',
6 => 'DSR Data set ready',
7 => 'SG Signal ground',
8 => 'CD Carrier detect',
9 => '+ voltage (testing)',
10 => '- voltage (testing)',
12 => 'SCD Secondary CD',
13 => 'SCS Secondary CTS',
14 => 'STD Secondary TD',
15 => 'TC Transmit clock',
16 => 'SRD Secondary RD',
17 => 'RC Receiver clock',
19 => 'SRS Secondary RTS',
20 => 'DTR Data terminal ready',
21 => 'SQD Signal quality detector',
22 => 'RI Ring indicator',
23 => 'DRS Data rate select',
24 => 'XTC External clock',
);
$vec->set($rs232{'RD Received data'}, 1);
$vec->get($rs232{'TC Transmit clock'});

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Task/Memory-layout-of-a-data-structure/Phix/memory-layout-of-a-data-structure.phix Normal file
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-->
<span style="color: #008080;">constant</span> <span style="color: #000000;">CD</span><span style="color: #0000FF;">=</span><span style="color: #000000;">1</span><span style="color: #0000FF;">,</span> <span style="color: #000000;">RD</span><span style="color: #0000FF;">=</span><span style="color: #000000;">2</span><span style="color: #0000FF;">,</span> <span style="color: #000000;">TD</span><span style="color: #0000FF;">=</span><span style="color: #000000;">3</span><span style="color: #0000FF;">,</span> <span style="color: #000000;">DTR</span><span style="color: #0000FF;">=</span><span style="color: #000000;">4</span><span style="color: #0000FF;">,</span> <span style="color: #0000FF;">...</span>
<span style="color: #004080;">atom</span> <span style="color: #000000;">addr</span> <span style="color: #0000FF;">=</span> <span style="color: #7060A8;">allocate</span><span style="color: #0000FF;">(</span><span style="color: #000000;">2</span><span style="color: #0000FF;">)</span> <span style="color: #000080;font-style:italic;">-- or wherever
--read</span>
<span style="color: #004080;">sequence</span> <span style="color: #000000;">bits</span> <span style="color: #0000FF;">=</span> <span style="color: #7060A8;">int_to_bits</span><span style="color: #0000FF;">(</span><span style="color: #000000;">peek2u</span><span style="color: #0000FF;">(</span><span style="color: #000000;">addr</span><span style="color: #0000FF;">),</span><span style="color: #000000;">16</span><span style="color: #0000FF;">)</span>
<span style="color: #004080;">integer</span> <span style="color: #000000;">dtr</span> <span style="color: #0000FF;">=</span> <span style="color: #000000;">bits</span><span style="color: #0000FF;">[</span><span style="color: #000000;">DTR</span><span style="color: #0000FF;">]</span>
<span style="color: #000080;font-style:italic;">--write</span>
<span style="color: #000000;">bits</span><span style="color: #0000FF;">[</span><span style="color: #000000;">DTR</span><span style="color: #0000FF;">]</span> <span style="color: #0000FF;">=</span> <span style="color: #000000;">1</span>
<span style="color: #7060A8;">poke2</span><span style="color: #0000FF;">(</span><span style="color: #000000;">addr</span><span style="color: #0000FF;">,</span><span style="color: #7060A8;">bits_to_int</span><span style="color: #0000FF;">(</span><span style="color: #000000;">bits</span><span style="color: #0000FF;">))</span>
<!--

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Task/Memory-layout-of-a-data-structure/PicoLisp/memory-layout-of-a-data-structure.l Normal file
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# Define bit constants
(for (N . Mask) '(CD RD TD DTR SG DSR RTS CTS RI)
(def Mask (>> (- 1 N) 1)) )
# Test if Clear to send
(when (bit? CTS Data)
... )

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Task/Memory-layout-of-a-data-structure/Python/memory-layout-of-a-data-structure.py Normal file
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from ctypes import Structure, c_int
rs232_9pin = "_0 CD RD TD DTR SG DSR RTS CTS RI".split()
rs232_25pin = ( "_0 PG TD RD RTS CTS DSR SG CD pos neg"
"_11 SCD SCS STD TC SRD RC"
"_18 SRS DTR SQD RI DRS XTC" ).split()
class RS232_9pin(Structure):
_fields_ = [(__, c_int, 1) for __ in rs232_9pin]
class RS232_25pin(Structure):
_fields_ = [(__, c_int, 1) for __ in rs232_25pin]

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Task/Memory-layout-of-a-data-structure/REXX/memory-layout-of-a-data-structure-1.rexx Normal file
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/* REXX ***************************************************************
* Decode Memory structure of RS-232 Plug Definition
* Not sure if I understood it completely :-) Open for corrections
* You never stop learning (as long as you live)
* 03.08.2012 Walter Pachl
**********************************************************************/
Call decode 'ABC'
Call decode 'XY'
Exit
decode:
Parse Arg c
cb=c2b(c)
If length(cb)=24 Then Do
Parse Var cb,
/* 1 - PG */ Protective ground +1,
/* 3 2 - TD */ Transmitted_data +1,
/* 2 3 - RD */ Received_data +1,
/* 7 4 - RTS */ Request_to_send +1,
/* 8 5 - CTS */ Clear_to_send +1,
/* 6 6 - DSR */ Data_set_ready +1,
/* 5 7 - SG */ Signal_ground +1,
/* 1 8 - CD */ Carrier_detect +1,
/* 9 - + */ plus_voltage +1,
/* 10 - - */ minus_voltage +1,
/* 11 - */ . +1,
/* 12 - SCD */ Secondary_CD +1,
/* 13 - SCS */ Secondary_CTS +1,
/* 14 - STD */ Secondary_TD +1,
/* 15 - TC */ Transmit_clock +1,
/* 16 - SRD */ Secondary_RD +1,
/* 17 - RC */ Receiver_clock +1,
/* 18 - */ . +1,
/* 19 - SRS */ Secondary_RTS +1,
/* 4 20 - DTR */ Data_terminal_ready +1,
/* 21 - SQD */ Signal_quality_detector+1,
/* 9 22 - RI */ Ring_indicator +1,
/* 23 - DRS */ Data_rate_select +1,
/* 24 - XTC */ External_clock +1
Say '24 bins:' cb
Say ' 1 - PG Protective ground ='Protective ground
Say ' 2 - TD Transmitted data ='Transmitted_data
Say ' 3 - RD Received data ='Received_data
Say ' 4 - RTS Request to send ='Request_to_send
Say ' 5 - CTS Clear to send ='Clear_to_send
Say ' 6 - DSR Data set ready ='Data_set_ready
Say ' 7 - SG Signal ground ='Signal_ground
Say ' 8 - CD Carrier detect ='Carrier_detect
Say ' 9 - + plus voltage ='plus_voltage
Say '10 - - minus voltage ='minus_voltage
Say ' '
Say '12 - SCD Secondary CD ='Secondary_CD
Say '13 - SCS Secondary CTS ='Secondary_CTS
Say '14 - STD Secondary TD ='Secondary_TD
Say '15 - TC Transmit clock ='Transmit_clock
Say '16 - SRD Secondary RD ='Secondary_RD
Say '17 - RC Receiver clock ='Receiver_clock
Say ' '
Say '19 - SRS Secondary RTS ='Secondary_RTS
Say '20 - DTR Data terminal ready ='Data_terminal_ready
Say '21 - SQD Signal quality detector ='Signal_quality_detector
Say '22 - RI Ring indicator ='Ring_indicator
Say '23 - DRS Data rate select ='Data_rate_select
Say '24 - XTC External hlock ='External_clock
End
Else Do
Parse Var cb,
/* 1 8 - CD */ Carrier_detect +1,
/* 2 3 - RD */ Received_data +1,
/* 3 2 - TD */ Transmitted_data +1,
/* 4 20 - DTR */ Data_terminal_ready +1,
/* 5 7 - SG */ Signal_ground +1,
/* 6 6 - DSR */ Data_set_ready +1,
/* 7 4 - RTS */ Request_to_send +1,
/* 8 5 - CTS */ Clear_to_send +1,
/* 9 22 - RI */ Ring_indicator +1
Say ' '
Say '9-bin:' left(cb,9)
Say ' 1 CD Carrier detect ='Carrier_detect
Say ' 2 RD Received data ='Received_data
Say ' 3 TD Transmitted data ='Transmitted_data
Say ' 4 DTR Data terminal ready ='Data_terminal_ready
Say ' 5 SG Signal ground ='Signal_ground
Say ' 6 DSR Data set ready ='Data_set_ready
Say ' 7 RTS Request to send ='Request_to_send
Say ' 8 CTS Clear to send ='Clear_to_send
Say ' 9 RI Ring indicator ='Ring_indicator
End
Return
c2b: Procedure
/* REXX ***************************************************************
* c2b Convert a character string to a bit string
* 03.08.2012 Walter Pachl
**********************************************************************/
Parse Arg c
x=c2x(c)
res=''
Do While x<>''
Parse Var x hb +1 x
Select
When hb='0' Then bs='0000'
When hb='1' Then bs='0001'
When hb='2' Then bs='0010'
When hb='3' Then bs='0011'
When hb='4' Then bs='0100'
When hb='5' Then bs='0101'
When hb='6' Then bs='0110'
When hb='7' Then bs='0111'
When hb='8' Then bs='1000'
When hb='9' Then bs='1001'
When hb='A' Then bs='1010'
When hb='B' Then bs='1011'
When hb='C' Then bs='1100'
When hb='D' Then bs='1101'
When hb='E' Then bs='1110'
When hb='F' Then bs='1111'
End
res=res||bs
End
Return res

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Task/Memory-layout-of-a-data-structure/REXX/memory-layout-of-a-data-structure-2.rexx Normal file
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/*REXX program displays which pins are active of a 9 or 24 pin RS-232 plug. */
call rs_232 24, 127 /*the value for an RS-232 24 pin plug.*/
call rs_232 24, '020304x' /* " " " " " " " " */
call rs_232 9, '10100000b' /* " " " " " 9 " " */
exit /*stick a fork in it, we're all done. */
/*──────────────────────────────────────────────────────────────────────────────────────*/
rs_232: arg ,x; parse arg pins,ox /*X is uppercased when using ARG. */
@. = '??? unassigned pin' /*assign a default for all the pins. */
@.24.1 = 'PG protective ground'
@.24.2 = 'TD transmitted data' ; @.9.3 = @.24.2
@.24.3 = 'RD received data' ; @.9.2 = @.24.3
@.24.4 = 'RTS request to send' ; @.9.7 = @.24.4
@.24.5 = 'CTS clear to send' ; @.9.8 = @.24.5
@.24.6 = 'DSR data set ready' ; @.9.6 = @.24.6
@.24.7 = 'SG signal ground' ; @.9.5 = @.24.7
@.24.8 = 'CD carrier detect' ; @.9.1 = @.24.8
@.24.9 = '+ positive voltage'
@.24.10 = '- negative voltage'
@.24.12 = 'SCD secondary CD'
@.24.13 = 'SCS secondary CTS'
@.24.14 = 'STD secondary td'
@.24.15 = 'TC transmit clock'
@.24.16 = 'SRD secondary RD'
@.24.17 = 'RC receiver clock'
@.24.19 = 'SRS secondary RTS'
@.24.20 = 'DTR data terminal ready' ; @.9.4 = @.24.20
@.24.21 = 'SQD signal quality detector'
@.24.22 = 'RI ring indicator' ; @.9.9 = @.24.22
@.24.23 = 'DRS data rate select'
@.24.24 = 'XTC external clock'
select
when right(x, 1)=='B' then bits= strip(x, 'T', "B")
when right(x, 1)=='X' then bits=x2b(strip(x, 'T', "X"))
otherwise bits=x2b( d2x(x) )
end /*select*/
say
bits=right(bits, pins, 0) /*right justify pin readings (values). */
say '───────── For a' pins "pin RS─232 plug, with a reading of: " ox
say
do j=1 for pins; z=substr(bits, j, 1); if z==0 then iterate
say right(j, 5) 'pin is "on": ' @.pins.j
end /*j*/
return

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Task/Memory-layout-of-a-data-structure/Racket/memory-layout-of-a-data-structure.rkt Normal file
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#lang racket
(require ffi/unsafe)
(define (_autobitmask l)
(_bitmask (append* (for/list ([x l] [i (in-naturals)]) `(,x = ,(expt 2 i))))))
(define _rs232 (_autobitmask '(CD RD TD DTR SG DSR RTS CTS RI )))
;; Usually it will get used when using foreign functions automatically, but
;; this demonstrates the conversions explicitly
(require (only-in '#%foreign ctype-scheme->c ctype-c->scheme))
((ctype-scheme->c _rs232) '(SG TD RI)) ; -> 276
((ctype-c->scheme _rs232) 276) ; -> '(TD SG RI)

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Task/Memory-layout-of-a-data-structure/Raku/memory-layout-of-a-data-structure-1.raku Normal file
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enum T_RS232 <
carrier_detect
received_data
transmitted_data
data_terminal_ready
signal_ground
data_set_ready
request_to_send
clear_to_send
ring_indicator
>;
my bit @signal[T_RS232];
@signal[signal_ground] = 1;

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Task/Memory-layout-of-a-data-structure/Raku/memory-layout-of-a-data-structure-2.raku Normal file
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$signal +|= 1 +< signal_ground;

30
Task/Memory-layout-of-a-data-structure/Ruby/memory-layout-of-a-data-structure.rb Normal file
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require 'bit-struct'
class RS232_9 < BitStruct
unsigned :cd, 1, "Carrier detect" #1
unsigned :rd, 1, "Received data" #2
unsigned :td, 1, "Transmitted data" #3
unsigned :dtr, 1, "Data terminal ready" #4
unsigned :sg, 1, "Signal ground" #5
unsigned :dsr, 1, "Data set ready" #6
unsigned :rts, 1, "Request to send" #7
unsigned :cts, 1, "Clear to send" #8
unsigned :ri, 1, "Ring indicator" #9
def self.new_with_int(value)
data = {}
fields.each_with_index {|f, i| data[f.name] = value[i]}
new(data)
end
end
num = rand(2**9 - 1)
puts "num = #{num}"
sample1 = RS232_9.new([("%09d" % num.to_s(2)).reverse].pack("B*"))
puts sample1.inspect_detailed
sample2 = RS232_9.new_with_int(num)
puts sample2.inspect_detailed
puts "CD is #{sample2.cd == 1 ? 'on' : 'off'}"

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Task/Memory-layout-of-a-data-structure/Scala/memory-layout-of-a-data-structure.scala Normal file
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object Rs232Pins9 extends App {
val (off: Boolean, on: Boolean) = (false, true)
val plug = new Rs232Pins9(carrierDetect = on, receivedData = on) // set first two pins, say
def toOnOff(b: Boolean) = if (b) "on" else "off"
class Rs232Pins9(
var carrierDetect: Boolean = off,
var receivedData: Boolean = off,
var transmittedData: Boolean = off,
var dataTerminalReady: Boolean = off,
var signalGround: Boolean = off,
var dataSetReady: Boolean = off,
var requestToSend: Boolean = off,
var clearToSend: Boolean = off,
var ringIndicator: Boolean = off
) {
def setPin(n: Int, v: Boolean) {
(n) match {
case 1 => carrierDetect = v
case 2 => receivedData = v
case 3 => transmittedData = v
case 4 => dataTerminalReady = v
case 5 => signalGround = v
case 6 => dataSetReady = v
case 7 => requestToSend = v
case 8 => clearToSend = v
case 9 => ringIndicator = v
}
}
}
// println(toOnOff(plug.component2())) // print value of pin 2 by number
plug.transmittedData = on // set pin 3 by name
plug.setPin(4, on) // set pin 4 by number
// println(toOnOff(plug.component3())) // print value of pin 3 by number
println(toOnOff(plug.dataTerminalReady)) // print value of pin 4 by name
println(toOnOff(plug.ringIndicator)) // print value of pin 9 by name
}

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Task/Memory-layout-of-a-data-structure/Tcl/memory-layout-of-a-data-structure.tcl Normal file
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set rs232_bits {CD RD TD DTR SG DSR RTS CTS RI}
proc rs232_encode args {
set res 0
foreach arg $args {
set pos [lsearch $::rs232_bits $arg]
if {$pos >=0} {set res [expr {$res | 1<<$pos}]}
}
return $res
}
proc rs232_decode int {
set res {}
set i -1
foreach bit $::rs232_bits {
incr i
if {$int & 1<<$i} {lappend res $bit}
}
return $res
}
#------------------------------ Test suite
foreach {test => expected} {
{rs232_encode CD} -> 1
{rs232_decode 1} -> CD
{rs232_encode CD RD TD} -> 7
{rs232_decode 7} -> {CD RD TD}
} {
catch $test res
if {$res ne $expected} {puts "$test -> $res, expected $expected"}
}

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Task/Memory-layout-of-a-data-structure/Wren/memory-layout-of-a-data-structure.wren Normal file
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import "/seq" for Lst
import "/fmt" for Fmt
var ON = true
var OFF = false
// Converts "ON"/"OFF" string to true/false.
var AsBool = Fn.new { |s| s == "ON" }
class RS232_9 {
static names { ["CD", "RD", "TD", "DTR", "SG", "DSR", "RTS", "CTS", "RI"] }
construct new() { _settings = [OFF] * 9 } // all pins OFF
// get pin setting as an ON/OFF string by pin name or number; returns null if invalid
[p] {
if (p is String) {
var ix = Lst.indexOf(RS232_9.names, p)
return (ix >= 0 && ix < 9) ? (_settings[ix] ? "ON" : "OFF") : null
}
if (p is Num) {
return (p.isInteger && p >= 1 && p <= 9) ? (_settings[p-1] ? "ON" : "OFF") : null
}
return null
}
// set pin by pin name or number; does nothing if invalid
[p] = (v) {
if (v.type == String && (v == "ON" || v == "OFF")) v = AsBool.call(v)
if (v.type != Bool) return
if (p is String) {
var ix = Lst.indexOf(RS232_9.names, p)
if (ix >= 0 && ix < 9) _settings[ix] = v
}
if (p is Num && p.isInteger && p >= 1 && p <= 9) _settings[p-1] = v
}
// prints all pin settings
toString { (1..9).map { |i| "%(i) %(Fmt.s(-3, RS232_9.names[i-1])) = %(this[i])" }.join("\n") }
}
var plug = RS232_9.new()
plug["CD"] = ON // set pin 1 by name
plug[3] = ON // set pin 3 by number
plug["DSR"] = "ON" // set pin 6 by name and using a string
System.print(plug) // print the state of the pins

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Task/Memory-layout-of-a-data-structure/XPL0/memory-layout-of-a-data-structure.xpl0 Normal file
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Assuming RS-232 pin 1 is connected to bit 0 of an I/O port et cetera, the
bits can be assigned names, such as these:
def CD=1<<0, RD=1<<1, TD=1<<2, DTR=1<<3, DSR=1<<4, RTS=1<<5, CTS=1<<6, RI=1<<7;
def RS232=$10;
The 'port' command can then be used to access these pin signals by name like this:
port(RS232):= TD ! RTS;
if port(RS232) & RD then ...
Note: The 'port' command is implemented in the Intel x86 versions but not
in the Raspberry Pi or Windows (EXPL32) versions.
]

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Task/Memory-layout-of-a-data-structure/Z80-Assembly/memory-layout-of-a-data-structure.z80 Normal file
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softRS232_LO equ &C000 ;%87654321 (each bit represents the state of a numbered pin)
softRS232_HI equ &C001 ;%-------9
ld hl,softRS232_LO ;memory location of soft RS232 port
ld c,&00 ;&00 = the port that the RS232 is connected to.
;This is just an example, the actual port number depends on where the hardware is connected.
outi ;send the value contained in softRS232_LO thru port &00
outi ;send the value contained in softRS232_HI thru port &00