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Ingy döt Net 2026-04-30 12:34:36 -04:00
parent 4bb20c9b71
commit cbaf4c4b64
12390 changed files with 318560 additions and 27248 deletions
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167
Task/Logical-operations/AArch64-Assembly/logical-operations.aarch64 Normal file
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/* ARM assembly AARCH64 Raspberry PI 3B */
/* program logicoper.s */
/*******************************************/
/* Constantes file */
/*******************************************/
/* for this file see task include a file in language AArch64 assembly*/
.include "../includeConstantesARM64.inc"
/*******************************************/
/* Initialized data */
/*******************************************/
.data
szMessStart: .asciz "Program 64 bits start.\n"
szMessFinOK: .asciz "Program normal end. \n"
szCarriageReturn: .asciz "\n"
szMessValue1: .asciz "Value 1 : \n"
szMessValue2: .asciz "Value 2 : \n"
szMessResultAnd: .asciz "Result of And : \n"
szMessResultOr: .asciz "Result of Or : \n"
szMessResultEor: .asciz "Result of Exclusive Or : \n"
szMessResultNot: .asciz "Result of Not : \n"
szMessResultClear: .asciz "Result of Bit Clear : \n"
/*******************************************/
/* UnInitialized data */
/*******************************************/
.bss
sZoneBin: .skip 80
/*******************************************/
/* code section */
/*******************************************/
.text
.global main
main: // entry of program
ldr x0,qAdrszMessStart
bl affichageMess
ldr x0,qAdrszMessValue1
bl affichageMess
mov x4,#0b1100 // binary value 1
mov x0,x4
bl affiche2
ldr x0,qAdrszMessValue2
bl affichageMess
mov x5,#0b0110 // binary value 2
mov x0,x5
bl affiche2
mov x0,x4
mov x1,x5
bl logicFunc
ldr x0,qAdrszMessFinOK
bl affichageMess
100: // standard end of the program */
mov x0,0 // return code
mov x8,EXIT // request to exit program
svc 0 // perform the system call
qAdrszMessStart: .quad szMessStart
qAdrszMessFinOK: .quad szMessFinOK
qAdrszMessValue1: .quad szMessValue1
qAdrszMessValue2: .quad szMessValue2
qAdrszMessResultAnd: .quad szMessResultAnd
qAdrszMessResultOr: .quad szMessResultOr
qAdrszMessResultEor: .quad szMessResultEor
qAdrszMessResultNot: .quad szMessResultNot
qAdrszMessResultClear: .quad szMessResultClear
/******************************************************************/
/* logics functions */
/******************************************************************/
/* x0 contains the first value */
/* x1 contains the second value */
logicFunc: // INFO: logicFunc
stp x2,lr,[sp,-16]! // save registers
stp x3,x4,[sp,-16]!
mov x4,x0 // save value 1
mov x5,x1 // save value 2
ldr x0,qAdrszMessResultAnd // and
bl affichageMess
mov x0,x4 // load value 1 in x0
and x0,x0,x5 // and value 2
bl affiche2
ldr x0,qAdrszMessResultOr // Or
bl affichageMess
mov x0,x4 // load value 1 in x0
orr x0,x0,x5 // or value 2
bl affiche2
ldr x0,qAdrszMessResultEor // xor
bl affichageMess
mov x0,x4 // load value 1 in x0
eor x0,x0,x5 // xor value 2
bl affiche2
ldr x0,qAdrszMessResultNot // not
bl affichageMess
mov x0,x4 // load value 1 in x0
mvn x0,x0 // not value 1
bl affiche2
ldr x0,qAdrszMessResultClear // bic
bl affichageMess
mov x0,x4 // load value 1 in x0
bic x0,x0,x5 // bic value 2
bl affiche2
100:
ldp x4,x5,[sp],16 // restaur registers
ldp x2,lr,[sp],16
ret
/******************************************************************/
/* register conversion in binary */
/******************************************************************/
/* x0 contains the register */
affiche2:
stp x1,lr,[sp,-16]! // save registers
ldr x1,qAdrsZoneBin
bl conversion2
ldr x0,qAdrsZoneBin
bl affichageMess
ldr x0,qAdrszCarriageReturn
bl affichageMess
100:
ldp x1,lr,[sp],16 // restaur 2 registres
ret // retour adresse lr x30
qAdrszCarriageReturn: .quad szCarriageReturn
/******************************************************************/
/* register conversion in binary */
/******************************************************************/
/* x0 contains the register */
/* x1 contains the address of receipt area */
conversion2:
stp x2,lr,[sp,-16]! // save registers
stp x3,x4,[sp,-16]! // save registers
clz x2,x0 // number of left zeros bits
mov x3,64
sub x2,x3,x2 // number of significant bits
strb wzr,[x1,x2] // store 0 final
sub x3,x2,1 // position counter of the written character
2: // loop
tst x0,1 // test first bit
lsr x0,x0,#1 // shift right one bit
bne 3f
mov x4,#48 // bit = 0 => character '0'
b 4f
3:
mov x4,#49 // bit = 1 => character '1'
4:
strb w4,[x1,x3] // character in reception area at position counter
sub x3,x3,#1
subs x2,x2,#1 // 0 bits ?
bgt 2b // no! loop
100:
ldp x3,x4,[sp],16 // restaur 2 registres
ldp x2,lr,[sp],16 // restaur 2 registres
ret // retour adresse lr x30
qAdrsZoneBin: .quad sZoneBin
/********************************************************/
/* File Include fonctions */
/********************************************************/
/* for this file see task include a file in language AArch64 assembly */
.include "../includeARM64.inc"

7
Task/Logical-operations/Ada/logical-operations.adb Normal file
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procedure Print_Logic(A : Boolean; B : Boolean) is
begin
Put_Line("A and B is " & Boolean'Image(A and B));
Put_Line("A or B is " & Boolean'Image(A or B));
Put_Line("A xor B is " & Boolean'Image(A xor B));
Put_Line("not A is " & Boolean'Image(not A));
end Print_Logic;

5
Task/Logical-operations/AppleScript/logical-operations.applescript Normal file
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on logic(a, b)
log a and b
log a or b
log not a
end logic

11
Task/Logical-operations/Ballerina/logical-operations.ballerina Normal file
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import ballerina/io;
function logic(boolean a, boolean b) {
io:println("a and b: ", a && b);
io:println("a or b: ", a || b);
io:println("not a: ", !a);
}
public function main() {
logic(true, false);
}

26
Task/Logical-operations/COBOL/logical-operations.cob Normal file
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IDENTIFICATION DIVISION.
PROGRAM-ID. print-logic.
DATA DIVISION.
LOCAL-STORAGE SECTION.
01 result PIC 1 USAGE BIT.
LINKAGE SECTION.
01 a PIC 1 USAGE BIT.
01 b PIC 1 USAGE BIT.
PROCEDURE DIVISION USING a, b.
COMPUTE result = a B-AND b
DISPLAY "a and b is " result
COMPUTE result = a B-OR b
DISPLAY "a or b is " result
COMPUTE result = B-NOT a
DISPLAY "Not a is " result
COMPUTE result = a B-XOR b
DISPLAY "a exclusive-or b is " result
GOBACK
.

7
Task/Logical-operations/Crystal/logical-operations.cr Normal file
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def show_logical_ops (a, b)
printf "%-5s && %-5s -> %s\n", a, b, a && b
printf "%-5s || %-5s -> %s\n", a, b, a || b
printf "!%-5s -> %s\n", a, !a
end
show_logical_ops false, true

4
Task/Logical-operations/EMal/logical-operations.emal
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fun logicOperations = void by logic a, logic b
writeLine("=== input values are " + a + ", " + b + " ===")
fun logicOperations ← void by logic a, logic b
writeLine("[ input values are " + a + ", " + b + " ]")
writeLine("a and b: " + (a and b))
writeLine(" a or b: " + (a or b))
writeLine(" not a: " + (not a))

6
Task/Logical-operations/Euphoria/logical-operations.eu Normal file
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procedure print_logic(integer a, integer b)
printf(1,"a and b is %d\n", a and b)
printf(1,"a or b is %d\n", a or b)
printf(1,"a xor b is %d\n", a xor b)
printf(1,"not a is %d\n", not a)
end procedure

7
Task/Logical-operations/PowerShell/logical-operations.ps1 Normal file
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function Test-Boolean ([bool] $a, [bool] $b) {
Write-Host "A and B: " ($a -and $b)
Write-Host "A or B: " ($a -or $b)
Write-Host "not A: " (-not $a)
Write-Host "not A: " (!$a)
Write-Host "A xor B: " ($a -xor $b)
}

129
Task/Logical-operations/RISC-V-Assembly/logical-operations.asm Normal file
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# riscv assembly raspberry pico2 rp2350
# program operlog.s
# connexion putty com3
/*********************************************/
/* CONSTANTES */
/********************************************/
/* for this file see risc-v task include a file */
.include "../../constantesRiscv.inc"
/*******************************************/
/* INITIALED DATAS */
/*******************************************/
.data
szMessStart: .asciz "Program riscv start.\r\n"
szCariageReturn: .asciz "\r\n"
szMessReg0: .asciz "Register s0:\r\n"
szMessReg1: .asciz "Register s1:\r\n"
szMessAnd: .asciz "And result:\r\n"
szMessOr: .asciz "Or result :\r\n"
szMessXor: .asciz "Xor result :\r\n"
szMessNot: .asciz "Not result :\r\n"
szMessNeg: .asciz "Neg result :\r\n"
.align 2
/*******************************************/
/* UNINITIALED DATA */
/*******************************************/
.bss
.align 2
sConvArea: .skip 24
sConvBinaire: .skip 36
/**********************************************/
/* SECTION CODE */
/**********************************************/
.text
.global main
main:
call stdio_init_all # général init
1: # start loop connexion
li a0,0 # raz argument register
call tud_cdc_n_connected # waiting for USB connection
beqz a0,1b # return code = zero ?
la a0,szMessStart # message address
call writeString # display message
la a0,szMessReg0 # message address
call writeString # display message
li s0,0b1100
mv a0,s0
call displayResult
la a0,szMessReg1 # message address
call writeString # display message
li s1,0b1001
mv a0,s1
call displayResult
la a0,szMessAnd # and
call writeString # display message
andi a0,s0,0b1001 # and immediat value
call displayResult
and a0,s0,s1 # register and
call displayResult
andn a0,s0,s1 # register and and not
call displayResult
la a0,szMessOr # or
call writeString # display message
ori a0,s0,0b1001 # or immediat value
call displayResult
or a0,s0,s1 # or register
call displayResult
orn a0,s0,s1 # or and not register
call displayResult
orc.b a0,s0 # OR-combine of bits within each byte. Generates a mask of nonzero bytes
call displayResult
la a0,szMessXor # xor
call writeString # display message
xori a0,s0,0b1001 # xor immediat value
call displayResult
xor a0,s0,s1 # xor register
call displayResult
xnor a0,s0,s1 # Bitwise XOR with inverted operand. Equivalently, bitwise NOT of bitwise XOR
call displayResult
la a0,szMessNot # not
call writeString # display message
not a0,s0 # not
call displayResult
la a0,szMessNeg # negation
call writeString # display message
neg a0,s0 # negation
call displayResult
call getchar
100: # final loop
j 100b
/**********************************************/
/* display binary Result */
/**********************************************/
/* a0 value */
.equ LGZONECONV, 20
displayResult:
addi sp, sp, -4 # reserve stack
sw ra, 0(sp)
la a1,sConvBinaire # conversion result address
call conversion2 # binary conversion
la a0,sConvBinaire # message address
call writeString # display message
la a0,szCariageReturn
call writeString
100:
lw ra, 0(sp)
addi sp, sp, 4
ret
/************************************/
/* file include Fonctions */
/***********************************/
/* for this file see risc-v task include a file */
.include "../../includeFunctions.s"

15
Task/Logical-operations/ReScript/logical-operations.res Normal file
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let logic = (a, b) => {
Js.log(string_of_bool(a) ++ " and " ++ string_of_bool(b) ++ " = " ++ string_of_bool(a && b))
Js.log(string_of_bool(a) ++ " or " ++ string_of_bool(b) ++ " = " ++ string_of_bool(a || b))
}
let logic2 = (a) =>
Js.log("not(" ++ string_of_bool(a) ++ ") = " ++ string_of_bool(!a))
logic(true, true)
logic(true, false)
logic(false, true)
logic(false, false)
logic2(true)
logic2(false)

13
Task/Logical-operations/Rebol/logical-operations.rebol Normal file
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logics: func [a [logic!] b [logic!]] [
print ['and tab a and b]
print ['or tab a or b]
print ['not tab not a]
print ['xor tab a xor b]
print ['and~ tab and~ a b]
print ['or~ tab or~ a b]
print ['xor~ tab xor~ a b]
print ['any tab any [a b]]
print ['all tab all [a b]]
]