langs a-z
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20
Task/Bitwise-operations/SystemVerilog/bitwise-operations-1.v
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Task/Bitwise-operations/SystemVerilog/bitwise-operations-1.v
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program main;
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initial begin
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bit [52:0] a,b,c;
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a = 53'h123476547890fe;
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b = 53'h06453bdef23ca6;
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c = a & b; $display("%h & %h = %h", a,b,c);
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c = a | b; $display("%h | %h = %h", a,b,c);
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c = a ^ b; $display("%h ^ %h = %h", a,b,c);
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c = ~ a; $display("~%h = %h", a, c);
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c = a << 5; $display("%h << 5 = %h", a, c);
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c = a >> 5; $display("%h >> 5 = %h", a, c);
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c = { a[53-23:0], a[52-:23] }; $display("%h rotate-left 23 = %h", a, c);
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c = { a[1:0], a[52:2] }; $display("%h rotate-right 2 = %h", a, c);
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end
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endprogram
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Task/Bitwise-operations/SystemVerilog/bitwise-operations-2.v
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Task/Bitwise-operations/SystemVerilog/bitwise-operations-2.v
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module rotate(in, out, shift);
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parameter BITS = 32;
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parameter SHIFT_BITS = 5;
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input [BITS-1:0] in;
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output [BITS-1:0] out;
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input [SHIFT_BITS-1:0] shift;
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always_comb foreach (out[i]) out[i] = in[ (i+shift) % BITS ];
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endmodule
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