Initial data commit

This commit is contained in:
Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 72d218235f
commit f23f22d71c
199087 changed files with 3378941 additions and 0 deletions

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ADD.L D0,D1 ; add two numbers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SUB.L D1,D0 ; subtract D1 from D0
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MULU D0,D1 ; multiply two unsigned numbers. Use MULS for signed numbers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
DIVU D1,D0 ; Divide D0 by D1. Use DIVS for signed numbers. Upper two bytes of D0 are the remainder, lower two are the integer quotient.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
MODULUS:
DIVU D1,D0
SWAP D0 ;swap the order of the 16-bit halves of D0.
RTS

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Exponent:
;raises D0 to the D1 power. No overflow protection.
MOVE.L D0,D2
SUBQ.L #1,D1
loop_exponent:
MULU D0,D2
DBRA D1,loop_exponent
;output is in D2
RTS