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Task/Arithmetic-Integer/Verilog/arithmetic-integer.v
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Task/Arithmetic-Integer/Verilog/arithmetic-integer.v
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module main;
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integer a, b;
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integer suma, resta, producto;
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integer division, resto, expo;
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initial begin
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a = -12;
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b = 7;
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suma = a + b;
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resta = a - b;
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producto = a * b;
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division = a / b;
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resto = a % b;
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expo = a ** b;
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$display("Siendo dos enteros a = -12 y b = 7");
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$display(" suma de a + b = ", suma);
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$display(" resta de a - b = ", resta);
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$display(" producto de a * b = ", producto);
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$display(" división de a / b = ", division);
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$display(" resto de a mod b = ", resto);
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$display("exponenciación a ^ b = ", expo);
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$finish ;
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end
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endmodule
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