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Initial data commit

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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 72d218235f
commit f23f22d71c
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6
Task/Conditional-structures/Verilog/conditional-structures-2.v Normal file
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case( expr_booleana )
valor1: command1;
valor2: command2;
...
default: commandN;
endcase