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Initial data commit

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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 72d218235f
commit f23f22d71c
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Task/Loops-For/Verilog/loops-for.v Normal file
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module main;
integer i, j;
initial begin
for(i = 1; i <= 5; i = i + 1) begin
for(j = 1; j <= i; j = j + 1) $write("*");
$display("");
end
$finish ;
end
endmodule