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Initial data commit

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Ingy döt Net 2023-07-01 11:58:00 -04:00
parent 72d218235f
commit f23f22d71c
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26
Task/Short-circuit-evaluation/Prolog/short-circuit-evaluation-1.pro Normal file
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short_circuit :-
( a_or_b(true, true) -> writeln('==> true'); writeln('==> false')) , nl,
( a_or_b(true, false)-> writeln('==> true'); writeln('==> false')) , nl,
( a_or_b(false, true)-> writeln('==> true'); writeln('==> false')) , nl,
( a_or_b(false, false)-> writeln('==> true'); writeln('==> false')) , nl,
( a_and_b(true, true)-> writeln('==> true'); writeln('==> false')) , nl,
( a_and_b(true, false)-> writeln('==> true'); writeln('==> false')) , nl,
( a_and_b(false, true)-> writeln('==> true'); writeln('==> false')) , nl,
( a_and_b(false, false)-> writeln('==> true'); writeln('==> false')) .
a_and_b(X, Y) :-
format('a(~w) and b(~w)~n', [X, Y]),
( a(X), b(Y)).
a_or_b(X, Y) :-
format('a(~w) or b(~w)~n', [X, Y]),
( a(X); b(Y)).
a(X) :-
format('a(~w)~n', [X]),
X.
b(X) :-
format('b(~w)~n', [X]),
X.

38
Task/Short-circuit-evaluation/Prolog/short-circuit-evaluation-2.pro Normal file
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?- short_circuit.
a(true) or b(true)
a(true)
==> true
a(true) or b(false)
a(true)
==> true
a(false) or b(true)
a(false)
b(true)
==> true
a(false) or b(false)
a(false)
b(false)
==> false
a(true) and b(true)
a(true)
b(true)
==> true
a(true) and b(false)
a(true)
b(false)
==> false
a(false) and b(true)
a(false)
==> false
a(false) and b(false)
a(false)
==> false
true.