*        Van der Corput sequence   31/01/2017
VDCS     CSECT
         USING  VDCS,R13           base register
         B      72(R15)            skip savearea
         DC     17F'0'             savearea
         STM    R14,R12,12(R13)    prolog
         ST     R13,4(R15)         " <-
         ST     R15,8(R13)         " ->
         LR     R13,R15            " addressability
         ZAP    B,=P'2'            b=2  (base)
         ZAP    M,=P'-1'           m=-1
         SR     R6,R6              i=0
LOOPI    CH     R6,=H'10'          do i=0 to 10
         BH     ELOOPI
         AP     M,=P'1'            w=m+1
         ZAP    V,=P'0'            v=0
         ZAP    S,=P'1'            s=1
         ZAP    N,M                n=m
WHILE    CP     N,=P'0'            do while n<>0
         BE     EWHILE
         MP     S,B                s=s*b
         ZAP    PL16,N             n
         DP     PL16,B             n/b
         ZAP    W,PL16+8(8)        w=n mod b
         MP     W,=P'100000'       *100000
         ZAP    PL16,W             w
         DP     PL16,S             w/s
         ZAP    W,PL16(8)          w=w/s
         AP     V,W                v=v+(n mod b)*100000/s
         ZAP    PL16,N             n
         DP     PL16,B             n/b
         ZAP    N,PL16(8)          n=n/b
         B      WHILE
EWHILE   XDECO  R6,XDEC            edit i
         MVC    PG+0(3),XDEC+9     output i
         MVC    PG+3(3),=C' 0.'
         UNPK   Z,V                unpack v
         OI     Z+L'Z-1,X'F0'      edit v
         MVC    PG+6(5),Z+11       output v  (v/100000)
         XPRNT  PG,L'PG            print buffer
         LA     R6,1(R6)           i=i+1
         B      LOOPI
ELOOPI   L      R13,4(0,R13)       epilog
         LM     R14,R12,12(R13)    " restore
         XR     R15,R15            " rc=0
         BR     R14                exit
B        DS     PL8
M        DS     PL8
V        DS     PL8
S        DS     PL8
N        DS     PL8
W        DS     PL8                packed
Z        DS     ZL16               zoned
PL16     DS     PL16               packed max
PG       DC     CL80' '            buffer
XDEC     DS     CL12               work area for xdeco
         YREGS
         END    VDCS