23 lines
401 B
VHDL
23 lines
401 B
VHDL
LIBRARY std;
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USE std.TEXTIO.all;
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entity test is
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end entity test;
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architecture beh of test is
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begin
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process
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variable line_in, line_out : line;
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variable a,b : integer;
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begin
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readline(INPUT, line_in);
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read(line_in, a);
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read(line_in, b);
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write(line_out, a+b);
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writeline(OUTPUT, line_out);
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wait; -- needed to stop the execution
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end process;
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end architecture beh;
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