11 lines
234 B
Verilog
11 lines
234 B
Verilog
module main;
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integer i;
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initial begin
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for (i = 1; i <= 10; i = i+1) begin
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if (i % 2 == 0) $display(i, " is even");
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else $display(i, " is odd");
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end
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$finish ;
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end
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endmodule
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