45 lines
939 B
VHDL
45 lines
939 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.NUMERIC_STD.all;
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entity tb is
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end tb ;
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architecture struct of tb is
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signal a : std_logic_vector(3 downto 0);
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signal b : std_logic_vector(3 downto 0);
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signal s : std_logic_vector(3 downto 0);
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signal v : std_logic;
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component four_bit_adder
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port (
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a : in std_logic_vector (3 downto 0);
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b : in std_logic_vector (3 downto 0);
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s : out std_logic_vector (3 downto 0);
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v : out std_logic
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);
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end component;
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begin
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proc_test: process
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begin
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for x in 0 to 15 loop
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for y in 0 to 15 loop
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a <= std_logic_vector(to_unsigned(x, 4));
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b <= std_logic_vector(to_unsigned(y, 4));
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wait for 100 ns;
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end loop;
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end loop;
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wait;
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end process;
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i_four_bit_adder : four_bit_adder
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port map (
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a => a,
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b => b,
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s => s,
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v => v
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);
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end struct;
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