12 lines
211 B
Verilog
12 lines
211 B
Verilog
module main;
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integer a, b;
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initial begin
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a = 1; //true
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b = 0; //false
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$display(a && b); //AND
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$display(a || b); //OR
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$display(!a); //NOT
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$finish ;
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end
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endmodule
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