14 lines
169 B
Verilog
14 lines
169 B
Verilog
module main;
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integer i;
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initial begin
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i = 1;
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$write(i);
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while(i % 6 != 0) begin
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i = i + 1;
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$write(i);
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end
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$finish ;
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end
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endmodule
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