19 lines
277 B
Verilog
19 lines
277 B
Verilog
module TEST;
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reg signed [11:0] y;
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initial begin
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y= sum(2, 2);
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y= sum(3, 2);
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y= sum(-3, 2);
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end
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function signed [11:0] sum;
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input signed [10:0] a, b;
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begin
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sum= a + b;
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$display("%d + %d = %d",a,b,sum);
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end
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endfunction
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endmodule
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