161 lines
2.7 KiB
VHDL
161 lines
2.7 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity four_bit_adder is
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port(
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a : in std_logic_vector (3 downto 0);
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b : in std_logic_vector (3 downto 0);
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s : out std_logic_vector (3 downto 0);
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v : out std_logic
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);
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end four_bit_adder ;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity fa is
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port(
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a : in std_logic;
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b : in std_logic;
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ci : in std_logic;
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co : out std_logic;
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s : out std_logic
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);
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end fa ;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity ha is
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port(
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a : in std_logic;
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b : in std_logic;
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c : out std_logic;
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s : out std_logic
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);
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end ha ;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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entity xor_gate is
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port(
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a : in std_logic;
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b : in std_logic;
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x : out std_logic
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);
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end xor_gate ;
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architecture struct of four_bit_adder is
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signal ci0 : std_logic;
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signal co0 : std_logic;
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signal co1 : std_logic;
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signal co2 : std_logic;
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component fa
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port (
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a : in std_logic ;
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b : in std_logic ;
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ci : in std_logic ;
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co : out std_logic ;
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s : out std_logic
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);
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end component;
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begin
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ci0 <= '0';
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i_fa0 : fa
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port map (
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a => a(0),
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b => b(0),
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ci => ci0,
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co => co0,
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s => s(0)
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);
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i_fa1 : fa
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port map (
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a => a(1),
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b => b(1),
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ci => co0,
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co => co1,
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s => s(1)
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);
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i_fa2 : fa
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port map (
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a => a(2),
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b => b(2),
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ci => co1,
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co => co2,
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s => s(2)
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);
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i_fa3 : fa
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port map (
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a => a(3),
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b => b(3),
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ci => co2,
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co => v,
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s => s(3)
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);
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end struct;
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architecture struct of fa is
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signal c1 : std_logic;
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signal c2 : std_logic;
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signal s1 : std_logic;
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component ha
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port (
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a : in std_logic ;
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b : in std_logic ;
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c : out std_logic ;
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s : out std_logic
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);
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end component;
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begin
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co <= c1 or c2;
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i_ha0 : ha
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port map (
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a => ci,
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b => a,
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c => c1,
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s => s1
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);
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i_ha1 : ha
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port map (
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a => s1,
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b => b,
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c => c2,
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s => s
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);
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end struct;
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architecture struct of ha is
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component xor_gate
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port (
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a : in std_logic;
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b : in std_logic;
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x : out std_logic
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);
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end component;
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begin
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c <= a and b;
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i_xor_gate : xor_gate
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port map (
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a => a,
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b => b,
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x => s
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);
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end struct;
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architecture rtl of xor_gate is
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begin
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x <= (a and not b) or (b and not a);
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end architecture rtl;
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