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Change HIP flags for DBCSR to use OFFLOAD_FLAGS
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5 changed files with 12 additions and 20 deletions
18
INSTALL.md
18
INSTALL.md
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@ -180,13 +180,14 @@ the FFTW3 threading library libfftw3_threads (or libfftw3_omp) is required.
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- Specify OFFLOAD_CC (e.g. `OFFLOAD_CC = nvcc`) and
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OFFLOAD_FLAGS (e.g. `OFFLOAD_FLAGS = -O3 -g -w --std=c++11`) variables.
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Remember to include the support for the C++11 standard.
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- Use the `-D__DBCSR_ACC` and `OFFLOAD_TARGET=cuda` to enable
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accelerator support for matrix multiplications.
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- Add `-lstdc++ -lcudart -lnvrtc -lcuda -lcublas` to LIBS.
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- Specify the GPU type (e.g. `GPUVER = P100`),
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possible values are K20X, K40, K80, P100, V100.
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- Specify the C++ compiler (e.g. `CXX = g++`). Remember to set the flags to
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support C++11 standard.
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- Specify the C++ compiler (e.g. `CXX = g++`) and the CXXFLAGS to support
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the C++11 standard.
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- Use `-D__PW_CUDA` for CUDA support for PW (gather/scatter/fft) calculations.
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- CUFFT 7.0 has a known bug and is therefore disabled by default.
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NVIDIA's webpage list a patch (an upgraded version cufft i.e. >= 7.0.35) -
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@ -329,12 +330,12 @@ The code for the grid backend was developed and tested on Mi100 but should work
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out of the box on Nvidia hardware as well.
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- USE `-D__GRID_HIP` to enable AMD GPU support for collocate and integrate
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runtines.
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rountines.
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- Add `GPUVER=Mi50, Mi60, Mi100`
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- Add 'OFFLOAD_CC = hipcc'
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- Add `OFFLOAD_CC = hipcc`
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- Add `-lamdhip64` to the `LIBS` variable
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- Add `OFFLOAD_FLAGS ='-fopenmp -m64 -pthread -fPIC -D__GRID_HIP -O2
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--offload-arch=gfx908 --rocm-path=$(ROCM_PATH)`' where 'ROCM_PATH' is the path
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--offload-arch=gfx908 --rocm-path=$(ROCM_PATH)'` where `ROCM_PATH` is the path
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where the rocm sdk resides. Architectures Mi100 (gfx908), Mi50 (gfx906)
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- the hip backend for the grid library supports nvidia hardware as well. It uses
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the same code and can be used to validate the backend in case of access to
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@ -342,11 +343,10 @@ out of the box on Nvidia hardware as well.
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and set the `OFFLOAD_FLAGS` with right `nvcc` parameters (see the cuda section
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of this document). The environment variable `HIP_PLATFORM` should be set to
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`HIP_PLATFORM=nvidia` to indicate to hipcc to use the nvcc compiler instead.
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- Specify the C++ compiler (e.g. `CXX = g++`). Remember to set the
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CXXFLAGS flags to support C++11 standard.
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- When the HIP backend is enabled for DBCSR using `-D__DBCSR_ACC`, then add
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`-D__HIP_PLATFORM_AMD__` to `CXXFLAGS` and `OFFLOAD_TARGET=hip`
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in the CP2K arch file.
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DBCSR will then be built with `CXX` and `CXXFLAGS` and avoid linking with
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multiple conflicting OpenMP runtimes.
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`-D__HIP_PLATFORM_AMD__` to `CXXFLAGS` and `OFFLOAD_TARGET=hip`.
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- Use `-D__OFFLOAD_PROFILING` to turn on the AMD ROC TX and Tracer libray.
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It requires to link `-lroctx64 -lroctracer64`.
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@ -24,6 +24,8 @@ DBCSR_ACCFLAGS := $(OFFLOAD_FLAGS)
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else ifeq (hip,$(DBCSR_USE_ACCEL))
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DBCSR_ACC := $(CXX)
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DBCSR_ACCFLAGS := $(CXXFLAGS)
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else
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$(error "Invalid OFFLOAD_TARGET=$(OFFLOAD_TARGET)")
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endif
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endif
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@ -8,15 +8,8 @@
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# For this reason, this Makefile must be compatible with the CP2K
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# compilation and tested within CP2K.
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#
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# You can compile DBCSR by running from the DBCSR main directory with:
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#
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# > make -f .cp2k/Makefile ARCH=<CP2K ARCH file>
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#
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# where we provide an ARCH file as described in the CP2K installation.
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#
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# The ARCH file can set the variables:
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#
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# CXX => C++ compiler, e.g. g++ or mpicxx
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# CC => C compiler, e.g. gcc or mpicc
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# FC => Fortran compiler, e.g. gfortran or mpifort
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# LD => Linker, e.g. gfortran or mpifort
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@ -117,7 +110,6 @@ endif
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else ifeq (hip,$(USE_ACCEL))
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override ACCFLAGS += -D__HIP
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FCFLAGS += -D__HIP
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CXXFLAGS += -D__HIP
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# OpenCL backend
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else ifeq (opencl,$(USE_ACCEL))
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CFLAGS += -D__OPENCL
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@ -1,3 +0,0 @@
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# This directory is used for the inclusion of the DBCSR library in CP2K
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It is not supported by DBCSR development
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@ -11,6 +11,7 @@ WFLAGS = ${WFLAGS}
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FCDEBFLAGS = ${FCDEBFLAGS}
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CFLAGS = ${CFLAGS}
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FCFLAGS = ${FCFLAGS}
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CXXFLAGS = ${CXXFLAGS}
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#
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LDFLAGS = ${LDFLAGS}
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LIBS = ${LIBS}
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