RosettaCodeData/Task/Bitwise-operations/SystemVerilog/bitwise-operations-2.v

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2013-04-10 22:43:41 -07:00
module rotate(in, out, shift);
parameter BITS = 32;
parameter SHIFT_BITS = 5;
input [BITS-1:0] in;
output [BITS-1:0] out;
input [SHIFT_BITS-1:0] shift;
always_comb foreach (out[i]) out[i] = in[ (i+shift) % BITS ];
endmodule