12 lines
242 B
Verilog
12 lines
242 B
Verilog
module rotate(in, out, shift);
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parameter BITS = 32;
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parameter SHIFT_BITS = 5;
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input [BITS-1:0] in;
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output [BITS-1:0] out;
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input [SHIFT_BITS-1:0] shift;
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always_comb foreach (out[i]) out[i] = in[ (i+shift) % BITS ];
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endmodule
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