September Morn Update
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Ingy döt Net
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6856 changed files with 141342 additions and 21127 deletions
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;Task:
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"''Simulate''" a four-bit adder "chip".
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"''Simulate''" a four-bit adder.
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This "chip" can be realized using four [[wp:Adder_(electronics)#Full_adder|1-bit full adder]]s.
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This design can be realized using four [[wp:Adder_(electronics)#Full_adder|1-bit full adder]]s.
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Each of these 1-bit full adders can be built with two [[wp:Adder_(electronics)#Half_adder|half adder]]s and an ''or'' [[wp:Logic gate|gate]]. Finally a half adder can be made using a ''xor'' gate and an ''and'' gate.
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The ''xor'' gate can be made using two ''not''s, two ''and''s and one ''or''.
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60
Task/Four-bit-adder/BASIC/four-bit-adder-1.basic
Normal file
60
Task/Four-bit-adder/BASIC/four-bit-adder-1.basic
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@ -0,0 +1,60 @@
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100 S$ = "1100 + 1100 = " : GOSUB 400
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110 S$ = "1100 + 1101 = " : GOSUB 400
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120 S$ = "1100 + 1110 = " : GOSUB 400
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130 S$ = "1100 + 1111 = " : GOSUB 400
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140 S$ = "1101 + 0000 = " : GOSUB 400
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150 S$ = "1101 + 0001 = " : GOSUB 400
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160 S$ = "1101 + 0010 = " : GOSUB 400
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170 S$ = "1101 + 0011 = " : GOSUB 400
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180 END
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400 A0 = VAL(MID$(S$, 4, 1))
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410 A1 = VAL(MID$(S$, 3, 1))
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420 A2 = VAL(MID$(S$, 2, 1))
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430 A3 = VAL(MID$(S$, 1, 1))
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440 B0 = VAL(MID$(S$, 11, 1))
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450 B1 = VAL(MID$(S$, 10, 1))
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460 B2 = VAL(MID$(S$, 9, 1))
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470 B3 = VAL(MID$(S$, 8, 1))
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480 GOSUB 600
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490 PRINT S$;
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REM 4 BIT PRINT
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500 PRINT C;S3;S2;S1;S0
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510 RETURN
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REM 4 BIT ADD
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REM ADD A3 A2 A1 A0 TO B3 B2 B1 B0
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REM RESULT IN S3 S2 S1 S0
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REM CARRY IN C
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600 C = 0
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610 A = A0 : B = B0 : GOSUB 700 : S0 = S
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620 A = A1 : B = B1 : GOSUB 700 : S1 = S
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630 A = A2 : B = B2 : GOSUB 700 : S2 = S
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640 A = A3 : B = B3 : GOSUB 700 : S3 = S
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650 RETURN
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REM FULL ADDER
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REM ADD A + B + C
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REM RESULT IN S
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REM CARRY IN C
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700 BH = B : B = C : GOSUB 800 : C1 = C
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710 A = S : B = BH : GOSUB 800 : C2 = C
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720 C = C1 OR C2
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730 RETURN
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REM HALF ADDER
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REM ADD A + B
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REM RESULT IN S
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REM CARRY IN C
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800 GOSUB 900 : S = C
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810 C = A AND B
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820 RETURN
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REM XOR GATE
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REM A XOR B
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REM RESULT IN C
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900 C = A AND NOT B
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910 D = B AND NOT A
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920 C = C OR D
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930 RETURN
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45
Task/Four-bit-adder/BASIC/four-bit-adder-2.basic
Normal file
45
Task/Four-bit-adder/BASIC/four-bit-adder-2.basic
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@% = 2
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PRINT "1100 + 1100 = ";
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PROC4bitadd(1,1,0,0, 1,1,0,0, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1100 + 1101 = ";
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PROC4bitadd(1,1,0,0, 1,1,0,1, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1100 + 1110 = ";
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PROC4bitadd(1,1,0,0, 1,1,1,0, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1100 + 1111 = ";
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PROC4bitadd(1,1,0,0, 1,1,1,1, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1101 + 0000 = ";
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PROC4bitadd(1,1,0,1, 0,0,0,0, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1101 + 0001 = ";
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PROC4bitadd(1,1,0,1, 0,0,0,1, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1101 + 0010 = ";
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PROC4bitadd(1,1,0,1, 0,0,1,0, e,d,c,b,a) : PRINT e,d,c,b,a
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PRINT "1101 + 0011 = ";
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PROC4bitadd(1,1,0,1, 0,0,1,1, e,d,c,b,a) : PRINT e,d,c,b,a
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END
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DEF PROC4bitadd(a3&, a2&, a1&, a0&, b3&, b2&, b1&, b0&, \
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\ RETURN c3&, RETURN s3&, RETURN s2&, RETURN s1&, RETURN s0&)
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LOCAL c0&, c1&, c2&
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PROCfulladder(a0&, b0&, 0, s0&, c0&)
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PROCfulladder(a1&, b1&, c0&, s1&, c1&)
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PROCfulladder(a2&, b2&, c1&, s2&, c2&)
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PROCfulladder(a3&, b3&, c2&, s3&, c3&)
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ENDPROC
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DEF PROCfulladder(a&, b&, c&, RETURN s&, RETURN c1&)
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LOCAL x&, y&, z&
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PROChalfadder(a&, c&, x&, y&)
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PROChalfadder(x&, b&, s&, z&)
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c1& = y& OR z&
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ENDPROC
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DEF PROChalfadder(a&, b&, RETURN s&, RETURN c&)
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s& = FNxorgate(a&, b&)
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c& = a& AND b&
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ENDPROC
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DEF FNxorgate(a&, b&)
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LOCAL c&, d&
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c& = a& AND NOT b&
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d& = b& AND NOT a&
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= c& OR d&
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42
Task/Four-bit-adder/Prolog/four-bit-adder.pro
Normal file
42
Task/Four-bit-adder/Prolog/four-bit-adder.pro
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@ -0,0 +1,42 @@
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% binary 4 bit adder chip simulation
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b_not(in(hi), out(lo)) :- !. % not(1) = 0
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b_not(in(lo), out(hi)). % not(0) = 1
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b_and(in(hi,hi), out(hi)) :- !. % and(1,1) = 1
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b_and(in(_,_), out(lo)). % and(anything else) = 0
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b_or(in(hi,_), out(hi)) :- !. % or(1,any) = 1
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b_or(in(_,hi), out(hi)) :- !. % or(any,1) = 1
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b_or(in(_,_), out(lo)). % or(anything else) = 0
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b_xor(in(A,B), out(O)) :-
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b_not(in(A), out(NotA)), b_not(in(B), out(NotB)),
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b_and(in(A,NotB), out(P)), b_and(in(NotA,B), out(Q)),
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b_or(in(P,Q), out(O)).
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b_half_adder(in(A,B), s(S), c(C)) :-
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b_xor(in(A,B),out(S)), b_and(in(A,B),out(C)).
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b_full_adder(in(A,B,Ci), s(S), c(C1)) :-
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b_half_adder(in(Ci, A), s(S0), c(C0)),
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b_half_adder(in(S0, B), s(S), c(C)),
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b_or(in(C0,C), out(C1)).
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b_4_bit_adder(in(A0,A1,A2,A3), in(B0,B1,B2,B3), out(S0,S1,S2,S3), c(V)) :-
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b_full_adder(in(A0,B0,lo), s(S0), c(C0)),
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b_full_adder(in(A1,B1,C0), s(S1), c(C1)),
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b_full_adder(in(A2,B2,C1), s(S2), c(C2)),
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b_full_adder(in(A3,B3,C2), s(S3), c(V)).
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test_add(A,B,T) :-
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b_4_bit_adder(A, B, R, C),
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writef('%w + %w is %w %w \t(%w)\n', [A,B,R,C,T]).
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go :-
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test_add(in(hi,lo,lo,lo), in(hi,lo,lo,lo), '1 + 1 = 2'),
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test_add(in(lo,hi,lo,lo), in(lo,hi,lo,lo), '2 + 2 = 4'),
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test_add(in(hi,lo,hi,lo), in(hi,lo,lo,hi), '5 + 9 = 14'),
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test_add(in(hi,hi,lo,hi), in(hi,lo,lo,hi), '11 + 9 = 20'),
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test_add(in(lo,lo,lo,hi), in(lo,lo,lo,hi), '8 + 8 = 16'),
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test_add(in(hi,hi,hi,hi), in(hi,lo,lo,lo), '15 + 1 = 16').
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63
Task/Four-bit-adder/Rust/four-bit-adder.rust
Normal file
63
Task/Four-bit-adder/Rust/four-bit-adder.rust
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@ -0,0 +1,63 @@
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// half adder with XOR and AND
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// SUM = A XOR B
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// CARRY = A.B
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fn half_adder(a: usize, b: usize) -> (usize, usize) {
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return (a ^ b, a & b);
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}
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// full adder as a combination of half adders
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// SUM = A XOR B XOR C
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// CARRY = A.B + B.C + C.A
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fn full_adder(a: usize, b: usize, c_in: usize) -> (usize, usize) {
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let (s0, c0) = half_adder(a, b);
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let (s1, c1) = half_adder(s0, c_in);
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return (s1, c0 | c1);
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}
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// A = (A3, A2, A1, A0)
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// B = (B3, B2, B1, B0)
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// S = (S3, S2, S1, S0)
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fn four_bit_adder (
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a: (usize, usize, usize, usize),
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b: (usize, usize, usize, usize)
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)
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->
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// 4 bit output, carry is ignored
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(usize, usize, usize, usize)
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{
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// lets have a.0 refer to the rightmost element
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let a = a.reverse();
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let b = b.reverse();
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// i would prefer a loop but that would abstract
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// the "connections of the constructive blocks"
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let (sum, carry) = half_adder(a.0, b.0);
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let out0 = sum;
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let (sum, carry) = full_adder(a.1, b.1, carry);
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let out1 = sum;
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let (sum, carry) = full_adder(a.2, b.2, carry);
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let out2 = sum;
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let (sum, _) = full_adder(a.3, b.3, carry);
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let out3 = sum;
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return (out3, out2, out1, out0);
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}
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fn main() {
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let a: (usize, usize, usize, usize) = (0, 1, 1, 0);
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let b: (usize, usize, usize, usize) = (0, 1, 1, 0);
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assert_eq!(four_bit_adder(a, b), (1, 1, 0, 0));
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// 0110 + 0110 = 1100
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// 6 + 6 = 12
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}
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// misc. traits to make our life easier
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trait Reverse<A, B, C, D> {
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fn reverse(self) -> (D, C, B, A);
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}
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// reverse a generic tuple of arity 4
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impl<A, B, C, D> Reverse<A, B, C, D> for (A, B, C, D) {
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fn reverse(self) -> (D, C, B, A){
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return (self.3, self.2, self.1, self.0)
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}
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}
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