12 lines
191 B
Verilog
12 lines
191 B
Verilog
module main;
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integer i, j;
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initial begin
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for(i = 1; i <= 5; i = i + 1) begin
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for(j = 1; j <= i; j = j + 1) $write("*");
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$display("");
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end
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$finish ;
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end
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endmodule
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